YD

Yael Duek-Golan

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #2,092,997 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8214782 Systems for total coverage analysis and ranking of circuit designs Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt 2012-07-03
7886242 Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt 2011-02-08