Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10303438 | Fused-multiply-add floating-point operations on 128 bit wide operands | Tina Babinsky, Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner | 2019-05-28 |
| 9703907 | RAS evaluation for circuit element | Christian Jacobi | 2017-07-11 |
| 9600616 | Assuring chip reliability with automatic generation of drivers and assertions | Eli Arbel, Erez Barak, Bodo Hoppe, Shiri Moran | 2017-03-21 |
| 9569573 | RAS evaluation for circuit element | Christian Jacobi | 2017-02-14 |
| 9483591 | Assuring chip reliability with automatic generation of drivers and assertions | Eli Arbel, Erez Barak, Bodo Hoppe, Shiri Moran | 2016-11-01 |
| 9471327 | Verifying forwarding paths in pipelines | Anand B. Arunagiri, Sujeet Kumar, Viresh Paruthi | 2016-10-18 |
| 9459878 | Verifying forwarding paths in pipelines | Anand B. Arunagiri, Sujeet Kumar, Viresh Paruthi | 2016-10-04 |
| 9274791 | Verification of a vector execution unit design | Maarten J. Boersma, Ulrike Schmidt | 2016-03-01 |
| 9268563 | Verification of a vector execution unit design | Maarten J. Boersma, Ulrike Schmidt | 2016-02-23 |
| 8918747 | Formal verification of a logic design | Maarten J. Boersma, Ulrike Schmidt | 2014-12-23 |
| 7949968 | Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring | Christian Jacobi, Viresh Paruthi, Matthias Pflanz, Kai Weber | 2011-05-24 |
| 7890903 | Method and system for formal verification of an electronic circuit design | Kai Weber, Matthias Pflanz, Christian Jacobi | 2011-02-15 |