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Controlling storage accesses for merge operations |
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Translation support for a virtual cache |
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Decentralized hot cache line tracking fairness mechanism |
Tu-An T. Nguyen, Matthias Klein, Gregory W. Alexander, Jason D. Kohl, Winston Herring +1 more |
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| 12014198 |
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| 11989071 |
Dynamic guard band with timing protection and with performance protection |
Tobias Webel, Alejandro Alberto Cook Lobo, Andrew A. Turner, Eberhard Engler, Edward C. McCain +12 more |
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Shadow pointer directory in an inclusive hierarchical cache |
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| 11960426 |
Cable pair concurrent servicing |
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| 11953982 |
Dynamic guard band with timing protection and with performance protection |
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| 11907125 |
Hot line fairness mechanism favoring software forward progress |
Gregory W. Alexander, Tu-An T. Nguyen, Deanna Postles Dunn Berger, Timothy C. Bronson |
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| 11907074 |
Low-latency deserializer having fine granularity and defective-lane compensation |
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| 11907124 |
Using a shadow copy of a cache in a cache hierarchy |
Yair Fried, Aaron Tsai, Eyal Naor, Timothy C. Bronson, Chung-Lung K. Shum |
2024-02-20 |
| 11892949 |
Reducing cache transfer overhead in a system |
Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai |
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| 11817697 |
Method to limit the time a semiconductor device operates above a maximum operating voltage |
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2023-11-14 |
| 11782836 |
Multiprocessor system cache management with non-authority designation |
Jason D. Kohl, Winston Herring, Tu-An T. Nguyen, Gregory W. Alexander, Timothy C. Bronson |
2023-10-10 |
| 11775445 |
Translation support for a virtual cache |
Markus Helms, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito +1 more |
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| 11762659 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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| 11675513 |
Selectively shearing data when manipulating data during record processing |
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| 11646861 |
Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes |
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| 11620231 |
Lateral persistence directory states |
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| 11593107 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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| 11586542 |
Reducing cache transfer overhead in a system |
Christian Zoellin, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai |
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| 11579874 |
Handling an input/output store instruction |
Christoph Raisch, Marco Kraemer, Frank Lehnert, Matthias Klein, Jonathan D. Bradbury +2 more |
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| 11520659 |
Refresh-hiding memory system staggered refresh |
Patrick J. Meaney, Glenn D. Gilda, David D. Cadigan, Lawrence W. Jones, Stephen J. Powell |
2022-12-06 |
| 11513704 |
Selectively evicting data from internal memory during record processing |
Scott B. Compton, Jeffrey R. Suarez, Matthew Michael Garcia Pardini |
2022-11-29 |
| 11403222 |
Cache structure using a logical directory |
Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai |
2022-08-02 |
