CW

Craig R. Walters

IBM: 48 patents #1,826 of 70,183Top 3%
WH Wheelock: 1 patents #16 of 26Top 65%
Overall (All Time): #55,569 of 4,157,543Top 2%
49
Patents All Time

Issued Patents All Time

Showing 25 most recent of 49 patents

Patent #TitleCo-InventorsDate
12288075 Instruction execution scheduling using a hit/miss predictor Dominic Ditomaso, David Trilla Rodriguez, Alper Buyuktosunoglu, Ram Sai Manoj Bamdhamravuri 2025-04-29
11620231 Lateral persistence directory states Ram Sai Manoj Bamdhamravuri, Christian Jacobi, Timothy C. Bronson, Gregory W. Alexander, Hieu T. Huynh +4 more 2023-04-04
11487672 Multiple copy scoping bits for cache memory Chunggeon Rhee, Ram Sai Manoj Bamdhamravuri, Timothy C. Bronson, Gregory W. Alexander 2022-11-01
11461151 Controller address contention assumption Robert J. Sonnelitter, III, Michael Fee, Arthur J. O'Neill, Matthias Klein 2022-10-04
11099966 Efficient generation of instrumentation data for direct memory access operations Matthias Klein, Deanna Postles Dunn Berger 2021-08-24
11010210 Controller address contention assumption Robert J. Sonnelitter, III, Michael Fee, Arthur J. O'Neill, Matthias Klein 2021-05-18
10915461 Multilevel cache eviction management Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Kevin Lopes, Michael A. Blake +4 more 2021-02-09
10884945 Memory state indicator check operations Pak-kin Mak, Timothy J. Slegel, Charles F. Webb 2021-01-05
10884946 Memory state indicator check operations Pak-kin Mak, Timothy J. Slegel, Charles F. Webb 2021-01-05
10884890 Accuracy sensitive performance counters Ram Sai Manoj Bamdhamravuri, Deanna Postles Dunn Berger, Mark R. Hodges, Kenneth D. Klapproth, Guy G. Tracy 2021-01-05
10795824 Speculative data return concurrent to an exclusive invalidate request Deanna Postles Dunn Berger, Christian Jacobi, Robert J. Sonnelitter, III 2020-10-06
10769068 Concurrent modification of shared cache line by multiple processors Nicholas C. Matsakis, Jane H. Bartik, Chung-Lung K. Shum, Elpida Tzortzatos 2020-09-08
10684968 Conditional memory spreading for heterogeneous memory sizes David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Patrick J. Meaney 2020-06-16
10635307 Memory state indicator Jane H. Bartik, Peter G. Sutton, Charles F. Webb 2020-04-28
10635308 Memory state indicator Jane H. Bartik, Peter G. Sutton, Charles F. Webb 2020-04-28
10599567 Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data Jane H. Bartik, Nicholas C. Matsakis, Chung-Lung K. Shum 2020-03-24
10572304 Dual/multi-mode processor pipelines sampling Deanna Postles Dunn Berger, Kathryn Marie Jackson, Joshua D. Massover, Gary E. Strait, Hanno Ulrich 2020-02-25
10540251 Accuracy sensitive performance counters Ram Sai Manoj Bamdhamravuri, Deanna Postles Dunn Berger, Mark R. Hodges, Kenneth D. Klapproth, Guy G. Tracy 2020-01-21
10417126 Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data Jane H. Bartik, Nicholas C. Matsakis, Chung-Lung K. Shum 2019-09-17
10379748 Predictive scheduler for memory rank switching James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney 2019-08-13
10255069 Cleared memory indicator Jane H. Bartik, Peter G. Sutton 2019-04-09
10248418 Cleared memory indicator Jane H. Bartik, Peter G. Sutton 2019-04-02
10176013 Dual/multi-mode processor pipeline sampling Deanna Postles Dunn Berger, Kathryn Marie Jackson, Joshua D. Massover, Gary E. Strait, Hanno Ulrich 2019-01-08
10175893 Predictive scheduler for memory rank switching James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney 2019-01-08
10084598 Authenticating features of virtual server system Khary J. Alexander, Reinhard T. Buendgen, K. Paul Muller, James A. O'Connor, William J. Rooney +2 more 2018-09-25