Issued Patents All Time
Showing 25 most recent of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10884946 | Memory state indicator check operations | Timothy J. Slegel, Craig R. Walters, Charles F. Webb | 2021-01-05 |
| 10884945 | Memory state indicator check operations | Timothy J. Slegel, Craig R. Walters, Charles F. Webb | 2021-01-05 |
| 10649908 | Non-disruptive clearing of varying address ranges from cache | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael A. Blake, Robert J. Sonnelitter, III, Guy G. Tracy +1 more | 2020-05-12 |
| 10628313 | Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache | Michael A. Blake, Timothy C. Bronson, Vesselina K. Papazova, Robert J. Sonnelitter, III | 2020-04-21 |
| 10628314 | Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache | Michael A. Blake, Timothy C. Bronson, Vesselina K. Papazova, Robert J. Sonnelitter, III | 2020-04-21 |
| 10572385 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Vesselina K. Papazova, Hanno Ulrich | 2020-02-25 |
| 10529396 | Preinstall of partial store cache lines | Ekaterina M. Ambroladze, Sascha Junghans, Matthias Klein, Robert J. Sonnelitter, III, Chad G. Wilson | 2020-01-07 |
| 10489294 | Hot cache line fairness arbitration in distributed modular SMP system | Michael A. Blake, Rebecca M. Gott, Vesselina K. Papazova | 2019-11-26 |
| 10437729 | Non-disruptive clearing of varying address ranges from cache | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael A. Blake, Robert J. Sonnelitter, III, Guy G. Tracy +1 more | 2019-10-08 |
| 10380020 | Achieving high bandwidth on ordered direct memory access write stream into a processor cache | Ekaterina M. Ambroladze, Timothy C. Bronson, Matthias Klein, Vesselina K. Papazova, Robert J. Sonnelitter, III +1 more | 2019-08-13 |
| 10379776 | Operation interlocking in an address-sliced cache system | Deanna Postles Dunn Berger, Michael A. Blake, Ashraf ElSharif, Kenneth D. Klapproth, Robert J. Sonnelitter, III +1 more | 2019-08-13 |
| 10339064 | Hot cache line arbitration | Michael A. Blake, Timothy C. Bronson, Jason D. Kohl, Vesselina K. Papazova | 2019-07-02 |
| 10331576 | Deadlock avoidance in a multi-processor computer system with extended cache line locking | Michael A. Blake, Robert J. Sonnelitter, III, Timothy W. Steele, Gary E. Strait, Poornima P Sulibele +1 more | 2019-06-25 |
| 10310982 | Target cache line arbitration within a processor cluster | Deanna Postles Dunn Berger, Johnathon J. Hoste, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2019-06-04 |
| 10055355 | Non-disruptive clearing of varying address ranges from cache | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael A. Blake, Robert J. Sonnelitter, III, Guy G. Tracy +1 more | 2018-08-21 |
| 9892043 | Nested cache coherency protocol in a tiered multi-node computer system | Garrett M. Drapala, William J. Lewis, Robert J. Sonnelitter, III | 2018-02-13 |
| 9858190 | Maintaining order with parallel access data streams | Ekaterina M. Ambroladze, Timothy C. Bronson, Garrett M. Drapala, Michael Fee, Matthias Klein +2 more | 2018-01-02 |
| 9852071 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Vesselina K. Papazova, Hanno Ulrich | 2017-12-26 |
| 9798663 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Vesselina K. Papazova, Hanno Ulrich | 2017-10-24 |
| 9727464 | Nested cache coherency protocol in a tiered multi-node computer system | Garrett M. Drapala, William J. Lewis, Robert J. Sonnelitter, III | 2017-08-08 |
| 9720833 | Nested cache coherency protocol in a tiered multi-node computer system | Garrett M. Drapala, William J. Lewis, Robert J. Sonnelitter, III | 2017-08-01 |
| 9600360 | Dynamic partial blocking of a cache ECC bypass | Michael Fee, Arthur J. O'Neill, Deanna Postles Dunn Berger | 2017-03-21 |
| 9600361 | Dynamic partial blocking of a cache ECC bypass | Michael Fee, Arthur J. O'Neill, Deanna Postles Dunn Berger | 2017-03-21 |
| 9594689 | Designated cache data backup during system operation | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Garrett M. Drapala, Michael Fee, Arthur J. O'Neill +1 more | 2017-03-14 |
| 9558119 | Main memory operations in a symmetric multiprocessing computer | Garrett M. Drapala, Arthur J. O'Neill, Craig R. Walters | 2017-01-31 |