Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11221794 | Memory array element sparing | Tim Bronson, Hieu T. Huynh | 2022-01-11 |
| 10956637 | Placement-driven generation of error detecting structures in integrated circuits | Ashraf ElSharif, Jason D. Kohl | 2021-03-23 |
| 10915461 | Multilevel cache eviction management | Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig R. Walters, Kevin Lopes +4 more | 2021-02-09 |
| 10884890 | Accuracy sensitive performance counters | Ram Sai Manoj Bamdhamravuri, Deanna Postles Dunn Berger, Mark R. Hodges, Guy G. Tracy, Craig R. Walters | 2021-01-05 |
| 10831661 | Coherent cache with simultaneous data requests in same addressable index | Ekaterina M. Ambroladze, Tim Bronson, Robert J. Sonnelitter, III, Deanna Postles Dunn Berger, Chad G. Wilson +3 more | 2020-11-10 |
| 10802966 | Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelization | Arun Kwangil Iyengar, Tim Bronson, Michael A. Blake, Vesselina K. Papazova, Arthur J. O'Neill +1 more | 2020-10-13 |
| 10540251 | Accuracy sensitive performance counters | Ram Sai Manoj Bamdhamravuri, Deanna Postles Dunn Berger, Mark R. Hodges, Guy G. Tracy, Craig R. Walters | 2020-01-21 |
| 10489292 | Ownership tracking updates across multiple simultaneous operations | Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Vesselina K. Papazova, Guy G. Tracy | 2019-11-26 |
| 10482015 | Ownership tracking updates across multiple simultaneous operations | Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Vesselina K. Papazova, Guy G. Tracy | 2019-11-19 |
| 10379776 | Operation interlocking in an address-sliced cache system | Deanna Postles Dunn Berger, Michael A. Blake, Ashraf ElSharif, Pak-kin Mak, Robert J. Sonnelitter, III +1 more | 2019-08-13 |
| 10325049 | Placement-driven generation of error detecting structures in integrated circuits | Ashraf ElSharif, Jason D. Kohl | 2019-06-18 |
| 9734110 | Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing | Garrett M. Drapala, Michael Fee, Robert J. Sonnelitter, III | 2017-08-15 |
| 9003127 | Storing data in a system memory for a subsequent cache flush | Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak, Vesselina K. Papazova | 2015-04-07 |
| 8990507 | Storing data in a system memory for a subsequent cache flush | Michael A. Blake, Pak-kin Mak, Timothy C. Bronson, Hieu T. Huynh, Vesselina K. Papazova | 2015-03-24 |
| 8930616 | System refresh in cache memory | Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh | 2015-01-06 |
| 8706972 | Dynamic mode transitions for cache instructions | Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2014-04-22 |
| 8639887 | Dynamically altering a pipeline controller mode based on resource availability | Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2014-01-28 |
| 8635409 | Dynamic mode transitions for cache instructions | Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2014-01-21 |
| 8478920 | Controlling data stream interruptions on a shared interface | Garrett M. Drapala, Robert J. Sonnelitter, III, Craig R. Walters | 2013-07-02 |
| 8458405 | Cache bank modeling with variable access and busy times | Timothy C. Bronson, Garrett M. Drapala, Hieu T. Huynh | 2013-06-04 |
| 8291157 | Concurrent refresh in cache memory | Timothy C. Bronson, Hieu T. Huynh, Charlie C. Hwang | 2012-10-16 |
| 7529799 | Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system | Manuel J. Alvarez, II, Sanjay Deshpande, David Mui | 2009-05-05 |
| 6904585 | Method for identification and removal of non-timing critical wire routes from congestion region | Mark A. Brittain, Vu T. Le, Joseph J. Palumbo | 2005-06-07 |
| 6816826 | Fully exhibiting asynchronous behavior in a logic network simulation | Flemming Andersen, Jason R. Baumgartner, Steven L. Roberts | 2004-11-09 |
| 6580288 | Multi-property microprocessor with no additional logic overhead to shared pins | — | 2003-06-17 |