Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11868259 | System coherency protocol | Robert J. Sonnelitter, III, Chad G. Wilson, Chakrapani Rayadurgam | 2024-01-09 |
| 11853212 | Preemptive tracking of remote requests for decentralized hot cache line fairness tracking | Tu-An T. Nguyen, Matthias Klein, Gregory W. Alexander, Jason D. Kohl | 2023-12-26 |
| 11042483 | Efficient eviction of whole set associated cache or selected range of addresses | Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Deanna Postles Dunn Berger | 2021-06-22 |
| 10915461 | Multilevel cache eviction management | Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig R. Walters, Kevin Lopes +4 more | 2021-02-09 |
| 10802966 | Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelization | Arun Kwangil Iyengar, Tim Bronson, Michael A. Blake, Arthur J. O'Neill, Jason D. Kohl +1 more | 2020-10-13 |
| 10628313 | Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache | Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Robert J. Sonnelitter, III | 2020-04-21 |
| 10628314 | Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache | Michael A. Blake, Timothy C. Bronson, Pak-kin Mak, Robert J. Sonnelitter, III | 2020-04-21 |
| 10572385 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Hanno Ulrich | 2020-02-25 |
| 10489292 | Ownership tracking updates across multiple simultaneous operations | Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Guy G. Tracy | 2019-11-26 |
| 10489294 | Hot cache line fairness arbitration in distributed modular SMP system | Michael A. Blake, Rebecca M. Gott, Pak-kin Mak | 2019-11-26 |
| 10482015 | Ownership tracking updates across multiple simultaneous operations | Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Guy G. Tracy | 2019-11-19 |
| 10380020 | Achieving high bandwidth on ordered direct memory access write stream into a processor cache | Ekaterina M. Ambroladze, Timothy C. Bronson, Matthias Klein, Pak-kin Mak, Robert J. Sonnelitter, III +1 more | 2019-08-13 |
| 10339064 | Hot cache line arbitration | Michael A. Blake, Timothy C. Bronson, Jason D. Kohl, Pak-kin Mak | 2019-07-02 |
| 9852071 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Hanno Ulrich | 2017-12-26 |
| 9798663 | Granting exclusive cache access using locality cache coherency state | Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Hanno Ulrich | 2017-10-24 |
| 9678873 | Early shared resource release in symmetric multiprocessing computer systems | Garrett M. Drapala, Robert J. Sonnelitter, III | 2017-06-13 |
| 9594646 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, John Steven Dodson | 2017-03-14 |
| 9535778 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, John Steven Dodson | 2017-01-03 |
| 9495231 | Reestablishing synchronization in a memory system | Glenn D. Gilda, Patrick J. Meaney, John Steven Dodson | 2016-11-15 |
| 9318171 | Dual asynchronous and synchronous memory system | Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson +4 more | 2016-04-19 |
| 9146864 | Address mapping including generic bits for universal addressing independent of memory type | Eric E. Retter, Patrick J. Meaney, Glenn D. Gilda, Mark R. Hodges | 2015-09-29 |
| 9142272 | Dual asynchronous and synchronous memory system | Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson +4 more | 2015-09-22 |
| 9104564 | Early data delivery prior to error detection completion | Glenn D. Gilda, Mark R. Hodges, Patrick J. Meaney | 2015-08-11 |
| 9092330 | Early data delivery prior to error detection completion | Glenn D. Gilda, Mark R. Hodges, Patrick J. Meaney | 2015-07-28 |
| 9037811 | Tagging in memory control unit (MCU) | Glenn D. Gilda, Mark R. Hodges, Eric E. Retter | 2015-05-19 |