Issued Patents All Time
Showing 25 most recent of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11960426 | Cable pair concurrent servicing | Rajat Rao, Patrick J. Meaney, Glenn D. Gilda, Michael Jason Cade, Robert J. Sonnelitter, III +3 more | 2024-04-16 |
| 11461151 | Controller address contention assumption | Robert J. Sonnelitter, III, Michael Fee, Craig R. Walters, Matthias Klein | 2022-10-04 |
| 11449397 | Cache array macro micro-masking | Gregory J. Fredeman, Glenn D. Gilda, Thomas E. Miller | 2022-09-20 |
| 11010210 | Controller address contention assumption | Robert J. Sonnelitter, III, Michael Fee, Craig R. Walters, Matthias Klein | 2021-05-18 |
| 10831661 | Coherent cache with simultaneous data requests in same addressable index | Ekaterina M. Ambroladze, Tim Bronson, Robert J. Sonnelitter, III, Deanna Postles Dunn Berger, Chad G. Wilson +3 more | 2020-11-10 |
| 10833707 | Error trapping in memory structures | Glenn D. Gilda | 2020-11-10 |
| 10824565 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2020-11-03 |
| 10802966 | Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelization | Arun Kwangil Iyengar, Tim Bronson, Michael A. Blake, Vesselina K. Papazova, Jason D. Kohl +1 more | 2020-10-13 |
| 10601448 | Reduced latency error correction decoding | Glenn D. Gilda, Patrick J. Meaney, Barry M. Trager | 2020-03-24 |
| 10402328 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2019-09-03 |
| 10394712 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2019-08-27 |
| 10310982 | Target cache line arbitration within a processor cluster | Deanna Postles Dunn Berger, Johnathon J. Hoste, Pak-kin Mak, Robert J. Sonnelitter, III | 2019-06-04 |
| 10169260 | Multiprocessor cache buffer management | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee | 2019-01-01 |
| 9898407 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2018-02-20 |
| 9892067 | Multiprocessor cache buffer management | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee | 2018-02-13 |
| 9886382 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Michael Fee, Robert J. Sonnelitter, III | 2018-02-06 |
| 9792213 | Mitigating busy time in a high performance cache | Deanna Postles Dunn Berger, Michael Fee, Christine C. Jones, Diana L. Orf, Robert J. Sonnelitter, III | 2017-10-17 |
| 9703661 | Eliminate corrupted portions of cache during runtime | Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee | 2017-07-11 |
| 9678848 | Eliminate corrupted portions of cache during runtime | Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee | 2017-06-13 |
| 9645904 | Dynamic cache row fail accumulation due to catastrophic failure | Michael Fee, Patrick J. Meaney | 2017-05-09 |
| 9600361 | Dynamic partial blocking of a cache ECC bypass | Michael Fee, Pak-kin Mak, Deanna Postles Dunn Berger | 2017-03-21 |
| 9600360 | Dynamic partial blocking of a cache ECC bypass | Michael Fee, Pak-kin Mak, Deanna Postles Dunn Berger | 2017-03-21 |
| 9594689 | Designated cache data backup during system operation | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Garrett M. Drapala, Michael Fee, Pak-kin Mak +1 more | 2017-03-14 |
| 9558119 | Main memory operations in a symmetric multiprocessing computer | Garrett M. Drapala, Pak-kin Mak, Craig R. Walters | 2017-01-31 |
| 9535787 | Dynamic cache row fail accumulation due to catastrophic failure | Michael Fee, Patrick J. Meaney | 2017-01-03 |