Issued Patents All Time
Showing 25 most recent of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11880304 | Cache management using cache scope designation | Taylor J. Pritchard, Aaron Tsai, Richard Joseph Branciforte, Ashraf ElSharif, Gregory W. Alexander +1 more | 2024-01-23 |
| 11681567 | Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive | Ralf Winkelmann, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger | 2023-06-20 |
| 11461151 | Controller address contention assumption | Robert J. Sonnelitter, III, Craig R. Walters, Arthur J. O'Neill, Matthias Klein | 2022-10-04 |
| 11321146 | Executing an atomic primitive in a multi-core processor system | Ralf Winkelmann, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger | 2022-05-03 |
| 11010210 | Controller address contention assumption | Robert J. Sonnelitter, III, Craig R. Walters, Arthur J. O'Neill, Matthias Klein | 2021-05-18 |
| 10824565 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2020-11-03 |
| 10402328 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2019-09-03 |
| 10394712 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2019-08-27 |
| 10176002 | Quiesce handling in multithreaded environments | Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro | 2019-01-08 |
| 10169260 | Multiprocessor cache buffer management | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill | 2019-01-01 |
| 10025608 | Quiesce handling in multithreaded environments | Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro | 2018-07-17 |
| 9929749 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Ronald J. Frishmuth, Mary P. Kusko, Cedric Lichtenau | 2018-03-27 |
| 9923579 | Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry | Ronald J. Frishmuth, Mary P. Kusko, Cedric Lichtenau | 2018-03-20 |
| 9915701 | Bypassing an encoded latch on a chip during a test-pattern scan | Ronald J. Frishmuth, Mary P. Kusko, Cedric Lichtenau | 2018-03-13 |
| 9910090 | Bypassing an encoded latch on a chip during a test-pattern scan | Ronald J. Frishmuth, Mary P. Kusko, Cedric Lichtenau | 2018-03-06 |
| 9898407 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2018-02-20 |
| 9892067 | Multiprocessor cache buffer management | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill | 2018-02-13 |
| 9886382 | Configuration based cache coherency protocol selection | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2018-02-06 |
| 9858190 | Maintaining order with parallel access data streams | Ekaterina M. Ambroladze, Timothy C. Bronson, Garrett M. Drapala, Matthias Klein, Pak-kin Mak +2 more | 2018-01-02 |
| 9792213 | Mitigating busy time in a high performance cache | Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III | 2017-10-17 |
| 9734110 | Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing | Garrett M. Drapala, Kenneth D. Klapproth, Robert J. Sonnelitter, III | 2017-08-15 |
| 9703661 | Eliminate corrupted portions of cache during runtime | Ekaterina M. Ambroladze, Michael A. Blake, Arthur J. O'Neill | 2017-07-11 |
| 9678848 | Eliminate corrupted portions of cache during runtime | Ekaterina M. Ambroladze, Michael A. Blake, Arthur J. O'Neill | 2017-06-13 |
| 9678830 | Recovery improvement for quiesced systems | Ute Gaertner, Lisa C. Heller, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-06-13 |
| 9665424 | Recovery improvement for quiesced systems | Ute Gaertner, Lisa C. Heller, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-05-30 |