JN

Jennifer A. Navarro

IBM: 24 patents #4,429 of 70,183Top 7%
📍 Poughkeepsie, NY: #170 of 1,613 inventorsTop 15%
🗺 New York: #5,468 of 115,490 inventorsTop 5%
Overall (All Time): #172,444 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDate
11036647 Suspending translation look-aside buffer purge execution in a multi-processor environment Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more 2021-06-15
10929312 Zone-SDID mapping scheme for TLB purges Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more 2021-02-23
10698835 Suspending translation look-aside buffer purge execution in a multi-processor environment Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more 2020-06-30
10353827 Zone-SDID mapping scheme for TLB purges Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more 2019-07-16
10353825 Suspending translation look-aside buffer purge execution in a multi-processor environment Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more 2019-07-16
10353828 Zone-SDID mapping scheme for TLB purges Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more 2019-07-16
10248575 Suspending translation look-aside buffer purge execution in a multi-processor environment Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more 2019-04-02
10176002 Quiesce handling in multithreaded environments Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert 2019-01-08
10025608 Quiesce handling in multithreaded environments Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert 2018-07-17
9678830 Recovery improvement for quiesced systems Michael Fee, Ute Gaertner, Lisa C. Heller, Frank Lehnert, Rebecca S. Wisniewski 2017-06-13
9665424 Recovery improvement for quiesced systems Michael Fee, Ute Gaertner, Lisa C. Heller, Frank Lehnert, Rebecca S. Wisniewski 2017-05-30
8407701 Facilitating quiesce operations within a logically partitioned computer system Ute Gaertner, Lisa C. Heller 2013-03-26
8332614 System, method and computer program product for providing a programmable quiesce filtering register Lisa C. Heller, Harald Boehm, Ute Gaertner, Timothy J. Slegel 2012-12-11
8285941 Enhancing timeliness of cache prefetching Kattamuri Ekanadham, Il Park, Chung-Lung K. Shum 2012-10-09
8140834 System, method and computer program product for providing a programmable quiesce filtering register Lisa C. Heller, Harald Boehm, Ute Gaertner, Timothy J. Slegel 2012-03-20
7890700 Method, system, and computer program product for cross-invalidation handling in a multi-level private cache Ka Shan Choy, Chung-Lung K. Shum, Aaron Tsai 2011-02-15
7089408 Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution Mark A. Check, Chung-Lung K. Shum 2006-08-08
7039762 Parallel cache interleave accesses with address-sliced directories Chung-Lung K. Shum, Aaron Tsai 2006-05-02
7035986 System and method for simultaneous access of the same line in cache storage Mark A. Check, Chung-Lung K. Shum, Timothy J. Slegel, Aaron Tsai 2006-04-25
6219758 False exception for cancelled delayed requests Barry W. Krumm, Chung-Lung K. Shum, Pak-kin Mak, Michael Fee 2001-04-17
6119219 System serialization with early release of individual processor Charles F. Webb, Dean G. Bair, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak +1 more 2000-09-12
6079013 Multiprocessor serialization with early release of processors Charles F. Webb, Dean G. Bair, Mark S. Farrell, Barry W. Krumm, Pak-kin Mak +1 more 2000-06-20
6035392 Computer with optimizing hardware for conditional hedge fetching into cache storage John S. Liptay, Mark A. Check, Barry W. Krumm, Charles F. Webb 2000-03-07
6026488 Method for conditional hedge fetching into cache storage John S. Liptay, Mark A. Check, Barry W. Krumm, Charles F. Webb 2000-02-15