Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11775444 | Fetch request arbiter | Willm Hinrichs, Markus Kaltenbach, Simon H. Friedmann, Joerg Deutschle | 2023-10-03 |
| 10956341 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2021-03-23 |
| 10929312 | Zone-SDID mapping scheme for TLB purges | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more | 2021-02-23 |
| 10635603 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2020-04-28 |
| 10621105 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2020-04-14 |
| 10380033 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2019-08-13 |
| 10380032 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2019-08-13 |
| 10353828 | Zone-SDID mapping scheme for TLB purges | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more | 2019-07-16 |
| 10353827 | Zone-SDID mapping scheme for TLB purges | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more | 2019-07-16 |
| 10176002 | Quiesce handling in multithreaded environments | Michael Fee, Ute Gaertner, Lisa C. Heller, Frank Lehnert, Jennifer A. Navarro | 2019-01-08 |
| 10140217 | Link consistency in a hierarchical TLB with concurrent table walks | Uwe Brandt, Frank Lehnert, Markus Helms, Martin Recktenwald | 2018-11-27 |
| 10127159 | Link consistency in a hierarchical TLB with concurrent table walks | Uwe Brandt, Frank Lehnert, Markus Helms, Martin Recktenwald | 2018-11-13 |
| 10083124 | Translating virtual memory addresses to physical addresses | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Frank Lehnert | 2018-09-25 |
| 10025608 | Quiesce handling in multithreaded environments | Michael Fee, Ute Gaertner, Lisa C. Heller, Frank Lehnert, Jennifer A. Navarro | 2018-07-17 |
| 9715458 | Multiprocessor computer system | Frank Lehnert | 2017-07-25 |
| 9658852 | Updating of shadow registers in N:1 clock domain | Frank Lehnert | 2017-05-23 |
| 8966221 | Translating translation requests having associated priorities | Ute Gaertner | 2015-02-24 |
| 8594321 | Apparatus and method for operating a symmetric cipher engine in cipher-block chaining mode | Ulrich Mayer, Bernd Nerz | 2013-11-26 |
| 8250336 | Method, system and computer program product for storing external device result data | Chung-Lung K. Shum, Brian D. Barrick, Aaron Tsai | 2012-08-21 |
| 8166249 | Performing a least recently used (LRU) algorithm for a co-processor | Siegmund Schlechter | 2012-04-24 |
| 8135960 | Multiprocessor electronic circuit including a plurality of processors and electronic data processing system | Thomas Fuchs, Ulrich Mayer, Chung-Lung K. Shum, Scott Barnett Swaney | 2012-03-13 |
| 5996063 | Management of both renamed and architected registers in a superscalar computer system | Ute Gaertner, Klaus J. Getzlaff, Erwin Pfeffer | 1999-11-30 |
| 5694400 | Checking data integrity in buffered data transmission | Gilles Gervais, Ingemar Holm, Helmut Kohler, Norbert Schumacher, Gerhard Zilles | 1997-12-02 |