UB

Uwe Brandt

IBM: 25 patents #4,217 of 70,183Top 7%
BA Buhler Ag: 2 patents #31 of 161Top 20%
Overall (All Time): #137,883 of 4,157,543Top 4%
28
Patents All Time

Issued Patents All Time

Showing 25 most recent of 28 patents

Patent #TitleCo-InventorsDate
11036647 Suspending translation look-aside buffer purge execution in a multi-processor environment Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler, Frank Lehnert +2 more 2021-06-15
10956341 Multi-engine address translation facility Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2021-03-23
10929312 Zone-SDID mapping scheme for TLB purges Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler +2 more 2021-02-23
10698835 Suspending translation look-aside buffer purge execution in a multi-processor environment Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler, Frank Lehnert +2 more 2020-06-30
10635603 Multi-engine address translation facility Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2020-04-28
10621105 Multi-engine address translation facility Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2020-04-14
10387326 Incorporating purge history into least-recently-used states of a translation lookaside buffer Markus Helms, Thomas Kohler, Frank Lehnert 2019-08-20
10380032 Multi-engine address translation facility Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2019-08-13
10380033 Multi-engine address translation facility Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2019-08-13
10353825 Suspending translation look-aside buffer purge execution in a multi-processor environment Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler, Frank Lehnert +2 more 2019-07-16
10353827 Zone-SDID mapping scheme for TLB purges Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler +2 more 2019-07-16
10353828 Zone-SDID mapping scheme for TLB purges Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler +2 more 2019-07-16
10289562 Incorporating purge history into least-recently-used states of a translation lookaside buffer Markus Helms, Thomas Kohler, Frank Lehnert 2019-05-14
10248575 Suspending translation look-aside buffer purge execution in a multi-processor environment Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler, Frank Lehnert +2 more 2019-04-02
10140217 Link consistency in a hierarchical TLB with concurrent table walks Frank Lehnert, Thomas Koehler, Markus Helms, Martin Recktenwald 2018-11-27
10127159 Link consistency in a hierarchical TLB with concurrent table walks Frank Lehnert, Thomas Koehler, Markus Helms, Martin Recktenwald 2018-11-13
10083124 Translating virtual memory addresses to physical addresses Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert 2018-09-25
9886395 Evicting cached stores Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast 2018-02-06
9720764 Uncorrectable memory errors in pipelined CPUs Michael Billeci, Christian Jacobi, Martin Recktenwald 2017-08-01
9658967 Evicting cached stores Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast 2017-05-23
9588893 Store cache for transactional memory Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast 2017-03-07
9588894 Store cache for transactional memory Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast 2017-03-07
8756538 Parsing data representative of a hardware design into commands of a hardware design environment Hans-Werner Anderson, Markus Buehler, Katherine Eve, Thomas Kalla, Jens Noack +1 more 2014-06-17
8560983 Incorporating synthesized netlists as subcomponents in a hierarchical custom design Thomas Makowski, Christoph Wandel, Holger Wetter 2013-10-15
7844871 Test interface for memory elements Stefan Buettner, Werner Juchmes, Juergen Pille 2010-11-30