Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11043938 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Harry Barowski, Michael Kugel, Wolfgang Penth | 2021-06-22 |
| 10984160 | Analysis and modification of circuit designs | Martin Bernhard Schmidt, Alexander Fritsch, Simon Brandl | 2021-04-20 |
| 10587248 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Harry Barowski, Michael Kugel, Wolfgang Penth | 2020-03-10 |
| 10367481 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Harry Barowski, Michael Kugel, Wolfgang Penth | 2019-07-30 |
| 9666278 | Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block | Alexander Fritsch, Shankar Kalyanasundaram, Rolf Sautter | 2017-05-30 |
| 9431096 | Hierarchical negative bitline boost write assist for SRAM memory devices | Alexander Fritsch, Michael Kugel, Rolf Sautter | 2016-08-30 |
| 8422313 | Reduced power consumption memory circuitry | Stefan Buettner, David A. Hrusecky, Wolfgang Penth, Rolf Sautter | 2013-04-16 |
| 7844871 | Test interface for memory elements | Uwe Brandt, Stefan Buettner, Juergen Pille | 2010-11-30 |
| 7558138 | Bypass circuit for memory arrays | Sebastian Ehrenreich, Atnje Mueller, Silke Salewski | 2009-07-07 |