Issued Patents All Time
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11881853 | True complement dynamic circuit and method for combining binary data | Michael Kugel, Rolf Sautter, Amira Rozenfeld | 2024-01-23 |
| 11557335 | Erasing a partition of an SRAM array with hardware support | Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille | 2023-01-17 |
| 11501196 | Qubit tuning by magnetic fields in superconductors | Albert Frisch, Markus Brink | 2022-11-15 |
| 11043938 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Werner Juchmes, Michael Kugel, Wolfgang Penth | 2021-06-22 |
| 10984843 | RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption | Martin Bernhard Schmidt, Simon Brandl, Wolfgang Penth | 2021-04-20 |
| 10956644 | Integrated circuit design changes using through-silicon vias | Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren, Sourav Saha | 2021-03-23 |
| 10832763 | Global bit line latch performance and power optimization | Martin Bernhard Schmidt, Alexander Fritsch, Matthias Hock | 2020-11-10 |
| 10593420 | Testing content addressable memory and random access memory | Sheldon B. Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2020-03-17 |
| 10587248 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Werner Juchmes, Michael Kugel, Wolfgang Penth | 2020-03-10 |
| 10534884 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2020-01-14 |
| 10417366 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-09-17 |
| 10366191 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-07-30 |
| 10367481 | Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature | Werner Juchmes, Michael Kugel, Wolfgang Penth | 2019-07-30 |
| 10333508 | Cross bar switch structure for highly congested environments | Kurt Lind, Friedrich Schroeder | 2019-06-25 |
| 10242140 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-26 |
| 10235487 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-19 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren, Sourav Saha | 2019-03-05 |
| 10223489 | Placement clustering-based white space reservation | Ajith Kumar M. Chandrasekaran, Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-03-05 |
| 10170199 | Testing content addressable memory and random access memory | Sheldon B. Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2019-01-01 |
| 10169519 | Area sharing between multiple large block synthesis (LBS) blocks | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2019-01-01 |
| 10079070 | Testing content addressable memory and random access memory | Sheldon B. Levenstein, Pradip Patel, Daniel Rodko, Gordon B. Sapp, Rolf Sautter | 2018-09-18 |
| 9946830 | Area sharing between multiple large block synthesis (LBS) blocks | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2018-04-17 |
| 9928329 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2018-03-27 |
| 9910948 | Layout of large block synthesis blocks in integrated circuits | Harald D. Folberth, Joachim Keinert, Sourav Saha | 2018-03-06 |
| 9733945 | Pipelining out-of-order instructions | Tim Niggemeier | 2017-08-15 |