Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956644 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2021-03-23 |
| 10740177 | Optimizing error correcting code in three-dimensional stacked memory | Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary, Kirk D. Peterson, John Bradley Deforge | 2020-08-11 |
| 10725678 | Power management for memory subsystems | Arindam Raychaudhuri, Diyanesh B. Chinnakkonda Vidyapoornachary, Anil B. Lingambudi | 2020-07-28 |
| 10534545 | Three-dimensional stacked memory optimizations for latency and power | Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Warren E. Maule, Kirk D. Peterson, Saravanan Sethuraman | 2020-01-14 |
| 10528288 | Three-dimensional stacked memory access optimization | Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Warren E. Maule, Kirk D. Peterson, Saravanan Sethuraman | 2020-01-07 |
| 10318689 | Integrated circuit logic extraction using cloning and expansion for engineering change order | George Antony, Ankit N. Kagliwal, Vinay K. Singh | 2019-06-11 |
| 10223491 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2019-03-05 |
| 10216885 | Adjusting scan connections based on scan control locations | Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, James D. Warnock | 2019-02-26 |
| 10168386 | Scan chain latency reduction | George Antony, Mary P. Kusko, Shrinivas Shenoy | 2019-01-01 |
| 10140414 | Critical region identification | George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha, Vinay K. Singh | 2018-11-27 |
| 9934348 | Adjusting scan connections based on scan control locations | Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, James D. Warnock | 2018-04-03 |
| 9659140 | Critical region identification | George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha, Vinay K. Singh | 2017-05-23 |
| 9633928 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2017-04-25 |
| 9569580 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2017-02-14 |
| 9557381 | Physically aware insertion of diagnostic circuit elements | William V. Huott, Mary P. Kusko, Robert C. Redburn, Andrew A. Turner | 2017-01-31 |
| 9501603 | Integrated circuit design changes using through-silicon vias | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2016-11-22 |
| 9412682 | Through-silicon via access device for integrated circuits | Harry Barowski, Joachim Keinert, Haoxing Ren, Sourav Saha | 2016-08-09 |
| 9378326 | Critical region identification | George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sourav Saha, Vinay K. Singh | 2016-06-28 |
| 9087168 | Optimizing operating range of an electronic circuit | John M. Cohn, David J. Hathaway, Diyanesh Babu C. Vidyapoornachary | 2015-07-21 |
| 8826208 | Computational thermal analysis during microchip design | Sourav Saha, Sumantra Sarkar | 2014-09-02 |
| 8638120 | Programmable gate array as drivers for data ports of spare latches | Ashish Jaitly, Thomas E. Rosser | 2014-01-28 |
| 8572536 | Spare latch distribution | George Antony, Thomas E. Rosser | 2013-10-29 |
| 8495553 | Native threshold voltage switching | George Antony, Alexander J. Suess | 2013-07-23 |