Issued Patents All Time
Showing 25 most recent of 168 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406119 | Processor chip timing adjustment enhancement | Todd A. Christensen, John E. Sheets, II, Eric Marz | 2025-09-02 |
| 12062657 | Long channel and short channel vertical FET co-integration for vertical FET VTFET | Terence B. Hook, Baozhen Li, Junli Wang | 2024-08-13 |
| 11875987 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Terry A. Spooner, Junli Wang | 2024-01-16 |
| 11462295 | Microchip level shared array repair | Timothy Erickson Meehan, John Bradley Deforge, William V. Huott, Uma Srinivasan, Hyong Uk Kim +2 more | 2022-10-04 |
| 11422597 | Predetermining separate thermal control points for chips of a multi-chip module | Eric Marz, Greg Abrami, Howard Victor Mahaney, Jr., William J. Anderl, Eric Jason Fluhr +1 more | 2022-08-23 |
| 11251179 | Long channel and short channel vertical FET co-integration for vertical FET VTFET | Terence B. Hook, Baozhen Li, Junli Wang | 2022-02-15 |
| 11227796 | Enhancement of iso-via reliability | Lawrence A. Clevenger, Baozhen Li, Xiao Hu Liu | 2022-01-18 |
| 11171064 | Metalization repair in semiconductor wafers | Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II | 2021-11-09 |
| 11171063 | Metalization repair in semiconductor wafers | Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II | 2021-11-09 |
| 11146251 | Performance-screen ring oscillator with switchable features | John Bradley Deforge, Theresa A. Newton, Andrew A. Turner, Terence B. Hook | 2021-10-12 |
| 11145543 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Terry A. Spooner, Junli Wang | 2021-10-12 |
| 11122680 | Passive methods of loose die identification | Nicolas Pizzuti, Tassbieh Hassan, Nathaniel Rex, Eric Marz, Christine Whiteside | 2021-09-14 |
| 11067895 | Method and structures for personalizing lithography | John Bradley Deforge, Bassem M. Hamieh, Terence B. Hook, Theresa A. Newton | 2021-07-20 |
| 11062993 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Terry A. Spooner, Junli Wang | 2021-07-13 |
| 11018084 | Managed integrated circuit power supply distribution | Anthony Gus Aipperspach, Jeffrey Douglas Brown, John E. Sheets, II | 2021-05-25 |
| 10964840 | Photodiode structures | John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe | 2021-03-30 |
| 10943972 | Precision BEOL resistors | Baozhen Li, John E. Sheets, II, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2021-03-09 |
| 10923575 | Low resistance contact for transistors | Lawrence A. Clevenger, Junli Wang, Baozhen Li, Terry A. Spooner, John E. Sheets, II | 2021-02-16 |
| 10896992 | Photodiode structures | John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe | 2021-01-19 |
| 10833025 | Compressive zone to reduce dicing defects | Thomas A. Wassick, Nicolas Pizzuti, Thomas M. Shaw | 2020-11-10 |
| 10784159 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II, Junli Wang, Chih-Chao Yang | 2020-09-22 |
| 10768226 | Testing mechanism for a proximity fail probability of defects across integrated chips | Alain G. Rwabukamba, Andrew A. Turner | 2020-09-08 |
| 10740177 | Optimizing error correcting code in three-dimensional stacked memory | Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary, Sridhar H. Rangarajan, John Bradley Deforge | 2020-08-11 |
| 10712498 | Shielding structures between optical waveguides | John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Jed H. Rankin | 2020-07-14 |
| 10699950 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II, Terry A. Spooner | 2020-06-30 |