Issued Patents All Time
Showing 25 most recent of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12389803 | Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer | Ashim Dutta, Shyng-Tsong Chen, Chih-Chao Yang | 2025-08-12 |
| 11901224 | Rework for metal interconnects using etch and thermal anneal | Prasad Bhosale, Chih-Chao Yang, Lawrence A. Clevenger | 2024-02-13 |
| 11875987 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2024-01-16 |
| 11735468 | Interconnect structures including self aligned vias | Chih-Chao Yang, Koichi Motoyama, Shyng-Tsong Chen | 2023-08-22 |
| 11417525 | Multiple patterning with mandrel cuts defined by block masks | Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Craig Child +4 more | 2022-08-16 |
| 11398378 | Metal on metal multiple patterning | Hsueh-Chung Chen, Ravi Prakash Srivastava, Somnath Ghosh, Nicholas V. LiCausi, Sean Reidy | 2022-07-26 |
| 11264276 | Interconnect integration scheme with fully self-aligned vias | Shyng-Tsong Chen | 2022-03-01 |
| 11244860 | Double patterning interconnect integration scheme with SAV | Shyng-Tsong Chen, Koichi Motoyama, Chih-Chao Yang | 2022-02-08 |
| 11227792 | Interconnect structures including self aligned vias | Chih-Chao Yang, Koichi Motoyama, Shyng-Tsong Chen | 2022-01-18 |
| 11145543 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2021-10-12 |
| 11062993 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2021-07-13 |
| 10957581 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2021-03-23 |
| 10957582 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2021-03-23 |
| 10923575 | Low resistance contact for transistors | Lawrence A. Clevenger, Junli Wang, Kirk D. Peterson, Baozhen Li, John E. Sheets, II | 2021-02-16 |
| 10886168 | Surface modified dielectric refill structure | Chih-Chao Yang, Koichi Motoyama, Shyng-Tsong Chen | 2021-01-05 |
| 10818494 | Metal on metal multiple patterning | Hsueh-Chung Chen, Ravi Prakash Srivastava, Somnath Ghosh, Nicholas V. LiCausi, Sean Reidy | 2020-10-27 |
| 10784119 | Multiple patterning with lithographically-defined cuts | Ravi Prakash Srivastava, Hsueh-Chung Chen, Steven McDermott, Martin O'Toole, Brendan O'Brien | 2020-09-22 |
| 10741439 | Merge mandrel features | Hsueh-Chung Chen, Martin O'Toole, Jason E. Stephens | 2020-08-11 |
| 10699950 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II | 2020-06-30 |
| 10658235 | Rework for metal interconnects using etch and thermal anneal | Prasad Bhosale, Chih-Chao Yang, Lawrence A. Clevenger | 2020-05-19 |
| 10636738 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2020-04-28 |
| 10615116 | Surface nitridation in metal interconnects | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2020-04-07 |
| 10566231 | Interconnect formation with chamferless via, and related interconnect | Martin O'Toole, Christopher J. Penny, Jae-ouk Choo, Adam L. da Silva, Craig Child +3 more | 2020-02-18 |
| 10468491 | Low resistance contact for transistors | Lawrence A. Clevenger, Junli Wang, Kirk D. Peterson, Baozhen Li, John E. Sheets, II | 2019-11-05 |
| 10460990 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2019-10-29 |