Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406119 | Processor chip timing adjustment enhancement | Todd A. Christensen, Eric Marz, Kirk D. Peterson | 2025-09-02 |
| 11171063 | Metalization repair in semiconductor wafers | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson | 2021-11-09 |
| 11171064 | Metalization repair in semiconductor wafers | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson | 2021-11-09 |
| 11018084 | Managed integrated circuit power supply distribution | Anthony Gus Aipperspach, Jeffrey Douglas Brown, Kirk D. Peterson | 2021-05-25 |
| 10943972 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2021-03-09 |
| 10923575 | Low resistance contact for transistors | Lawrence A. Clevenger, Junli Wang, Kirk D. Peterson, Baozhen Li, Terry A. Spooner | 2021-02-16 |
| 10784159 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang, Chih-Chao Yang | 2020-09-22 |
| 10699950 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2020-06-30 |
| 10580730 | Managed integrated circuit power supply distribution | Anthony Gus Aipperspach, Jeffrey Douglas Brown, Kirk D. Peterson | 2020-03-03 |
| 10468491 | Low resistance contact for transistors | Lawrence A. Clevenger, Junli Wang, Kirk D. Peterson, Baozhen Li, Terry A. Spooner | 2019-11-05 |
| 10361265 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2019-07-23 |
| 10340330 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2019-07-02 |
| 10332956 | Precision beol resistors | Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2019-06-25 |
| 10332955 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang | 2019-06-25 |
| 10256145 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang, Chih-Chao Yang | 2019-04-09 |
| 9997408 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2018-06-12 |
| 9966308 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang, Chih-Chao Yang | 2018-05-08 |
| 9570388 | FinFET power supply decoupling | Todd A. Christensen | 2017-02-14 |
| 9520876 | Power gating and clock gating in wiring levels | Nathaniel R. Chadwick, Tassbieh Hassan, Kirk D. Peterson, Christine Whiteside | 2016-12-13 |
| 9455251 | Decoupling capacitor using finFET topology | Todd A. Christensen | 2016-09-27 |
| 9405311 | Bias-temperature induced damage mitigation circuit | David M. Onsongo, David P. Paulsen, Kirk D. Peterson | 2016-08-02 |
| 9401643 | Bias-temperature induced damage mitigation circuit | David M. Onsongo, David P. Paulsen, Kirk D. Peterson | 2016-07-26 |
| 8531203 | Mask alignment, rotation and bias monitor utilizing threshold voltage dependence | Todd A. Christensen, Matthew James Paschal | 2013-09-10 |
| 8300450 | Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation | Todd A. Christensen | 2012-10-30 |