| 12506080 |
Reduced capacitance between power via bar and gates |
Ruinan Xie, Ki-Hyouk Choi, Reinaldo Vega, Albert M. Chu, Nicholas Anthony Lanzillo |
2025-12-23 |
|
| 12500144 |
Backside self aligned skip via |
Ruinan Xie, Biswanath Senapati, David Wolpert, Nicholas Anthony Lanzillo, Leon Sigal +3 more |
2025-12-16 |
|
| 12494428 |
Airgap spacer for power via |
Ruinan Xie, Nicholas Anthony Lanzillo, Ki-Hyouk Choi, Huei Ching Huang |
2025-12-09 |
|
| 12489035 |
Semiconductor passive device integration for silicon-on-insulator substrate |
Ruinan Xie, Ki-Hyouk Choi, Tenko Yamashita, John P. Arnold |
2025-12-02 |
|
| 12482746 |
Early backside first power delivery network |
Brent A. Anderson, Christopher J. Penny, Nicholas Anthony Lanzillo |
2025-11-25 |
|
| 12484248 |
Source/drain contact at tight cell boundary |
Ruinan Xie, Nicholas Anthony Lanzillo, Brent A. Anderson, Reinaldo Vega, Albert M. Chu |
2025-11-25 |
|
| 12469777 |
BEOL interconnect subtractive etch super via |
Prasad Bhosale, Nicholas Anthony Lanzillo, Michael Rizzolo |
2025-11-11 |
|
| 12464960 |
Metal hard mask integration for active device structures |
Michael Rizzolo, Takashi Ando, Kevin W. Brew |
2025-11-04 |
|
| 12463128 |
Interconnect structures with vias having vertical and horizontal sections |
Ruinan Xie, Albert M. Chu, Brent A. Anderson, Nicholas Anthony Lanzillo |
2025-11-04 |
|
| 12463130 |
Wrap around metal via structure |
Reinaldo Vega, Nicholas Anthony Lanzillo, Albert M. Chu, Ruinan Xie, Brent A. Anderson |
2025-11-04 |
|
| 12457793 |
Vertical transport field effect transistor (VTFET) with backside wraparound contact |
Ruinan Xie, Brent A. Anderson, Nicholas Anthony Lanzillo, Reinaldo Vega, Albert M. Chu |
2025-10-28 |
|
| 12439608 |
MRAM integration with self-aligned direct back side contact |
Ruinan Xie, Nicholas Anthony Lanzillo, Koichi Motoyama, Brent A. Anderson, Michael Rizzolo |
2025-10-07 |
|
| 12424557 |
Dual structured buried rail |
Huai Huang, Nicholas Anthony Lanzillo, Ruilong Xie, Hosadurga Shobha |
2025-09-23 |
|
| 12424550 |
Buried metal signal rail for memory arrays |
Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Geoffrey Burr, Kohji Hosokawa |
2025-09-23 |
|
| 12424549 |
Skip-level TSV with hybrid dielectric scheme for backside power delivery |
Nicholas Anthony Lanzillo, Ruilong Xie, Huai Huang, Hosadurga Shobha |
2025-09-23 |
|
| 12419079 |
Field effect transistor with backside source/drain |
Ruilong Xie, Brent A. Anderson, Kisik Choi, Su Chen Fan, Shogo Mochizuki +1 more |
2025-09-16 |
|
| 12417979 |
Pass-through wiring in notched interconnect |
Nicholas Anthony Lanzillo, Albert M. Chu, Ruilong Xie, Reinaldo Vega, Brent A. Anderson |
2025-09-16 |
|
| 12417963 |
Isolation rail between backside power rails |
Nicholas Anthony Lanzillo, Hosadurga Shobha, Ruilong Xie, Baozhen Li |
2025-09-16 |
|
| 12412830 |
Semiconductor device with power via |
Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega +2 more |
2025-09-09 |
|
| 12412836 |
Backside power plane |
Ruilong Xie, Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang |
2025-09-09 |
|
| 12412833 |
TopVia interconnect with enlarged via top |
Chen Zhang, Brent A. Anderson, Nicholas Anthony Lanzillo |
2025-09-09 |
|
| 12402546 |
Composite material phase change memory cell |
Timothy Mathew Philip, Kevin W. Brew, Caitlin Camille Stuckey, Rebecca Martin, Robert R. Robison |
2025-08-26 |
|
| 12400960 |
Vertical-transport field-effect transistor with backside gate contact |
Brent A. Anderson, Albert M. Chu, Ruilong Xie, Nicholas Anthony Lanzillo, Reinaldo Vega |
2025-08-26 |
|
| 12400871 |
Metal lines with low via-to-via spacing |
Daniel James Dechene, Somnath Ghosh, Hsueh-Chung Chen, Carl Radens |
2025-08-26 |
|
| 12387983 |
Forming self-aligned vias and air-gaps in semiconductor fabrication |
Carl Radens, John H. Zhang |
2025-08-12 |
|
