| 12424549 |
Skip-level TSV with hybrid dielectric scheme for backside power delivery |
Nicholas Anthony Lanzillo, Ruilong Xie, Huai Huang, Hosadurga Shobha |
2025-09-23 |
| 12424557 |
Dual structured buried rail |
Huai Huang, Nicholas Anthony Lanzillo, Ruilong Xie, Hosadurga Shobha |
2025-09-23 |
| 12424550 |
Buried metal signal rail for memory arrays |
Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Geoffrey Burr, Kohji Hosokawa |
2025-09-23 |
| 12419079 |
Field effect transistor with backside source/drain |
Ruilong Xie, Brent A. Anderson, Kisik Choi, Su Chen Fan, Shogo Mochizuki +1 more |
2025-09-16 |
| 12417979 |
Pass-through wiring in notched interconnect |
Nicholas Anthony Lanzillo, Albert M. Chu, Ruilong Xie, Reinaldo Vega, Brent A. Anderson |
2025-09-16 |
| 12417963 |
Isolation rail between backside power rails |
Nicholas Anthony Lanzillo, Hosadurga Shobha, Ruilong Xie, Baozhen Li |
2025-09-16 |
| 12412833 |
TopVia interconnect with enlarged via top |
Chen Zhang, Brent A. Anderson, Nicholas Anthony Lanzillo |
2025-09-09 |
| 12412836 |
Backside power plane |
Ruilong Xie, Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang |
2025-09-09 |
| 12412830 |
Semiconductor device with power via |
Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega +2 more |
2025-09-09 |
| 12400960 |
Vertical-transport field-effect transistor with backside gate contact |
Brent A. Anderson, Albert M. Chu, Ruilong Xie, Nicholas Anthony Lanzillo, Reinaldo Vega |
2025-08-26 |
| 12400871 |
Metal lines with low via-to-via spacing |
Daniel James Dechene, Somnath Ghosh, Hsueh-Chung Chen, Carl Radens |
2025-08-26 |
| 12402546 |
Composite material phase change memory cell |
Timothy Mathew Philip, Kevin W. Brew, Caitlin Camille Stuckey, Rebecca Martin, Robert R. Robison |
2025-08-26 |
| 12387983 |
Forming self-aligned vias and air-gaps in semiconductor fabrication |
Carl Radens, John H. Zhang |
2025-08-12 |
| 12363965 |
Stacked transistor layout for improved cell height scaling |
Ruilong Xie, Nicholas Anthony Lanzillo, Albert M. Chu, Daniel James Dechene, Eric Miller |
2025-07-15 |
| 12341066 |
Advanced metal interconnect |
Ashim Dutta, Chih-Chao Yang, Ruilong Xie |
2025-06-24 |
| 12336294 |
Gate-cut and separation techniques for enabling independent gate control of stacked transistors |
Ruilong Xie, Nicolas Loubet, Julien Frougier, Prasad Bhosale, Junli Wang +2 more |
2025-06-17 |
| 12334442 |
Dielectric caps for power and signal line routing |
Nicholas Anthony Lanzillo, Ruilong Xie, Hosadurga Shobha, Huai Huang |
2025-06-17 |
| 12272648 |
Semiconductor device having a backside power rail |
Ruilong Xie, Junli Wang, Julien Frougier, Dechao Guo |
2025-04-08 |
| 12261056 |
Top via patterning using metal as hard mask and via conductor |
Nicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Chanro Park |
2025-03-25 |
| 12243819 |
Single-mask alternating line deposition |
Brent A. Anderson, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison |
2025-03-04 |
| 12230544 |
Stacked transistors with different channel widths |
Kangguo Cheng, Balasubramanian Pranatharthiharan, John H. Zhang |
2025-02-18 |
| 12218003 |
Selective ILD deposition for fully aligned via with airgap |
Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Michael Rizzolo, Hosadurga Shobha |
2025-02-04 |
| 12208386 |
3D nanochannel interleaved devices |
Kangguo Cheng, Donald F. Canaperi, Shawn P. Fetterolf |
2025-01-28 |
| 12156486 |
Horizontal RRAM device and architecture for variability reduction |
Timothy Mathew Philip, Christopher J. Penny, Nicholas Anthony Lanzillo, Youngseok Kim |
2024-11-26 |
| 12148682 |
Memory cell in wafer backside |
Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Geoffrey Burr, Kohji Hosokawa |
2024-11-19 |
