Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
CP

Christopher J. Penny — 167 Patents

IBM: 151 patents #287 of 70,183Top 1%
TETessera: 11 patents #38 of 271Top 15%
ASAdeia Semiconductor Solutions: 2 patents #9 of 57Top 20%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Saratoga Springs, NY: #3 of 363 inventorsTop 1%
New York: #211 of 115,490 inventorsTop 1%
Overall (All Time): #4,975 of 4,157,543Top 1%
167 Patents All Time
Christopher J. Penny has been granted 167 US patents while listed as an inventor at IBM. The first was granted in 2009 and the most recent in November 2025. Christopher J. Penny ranks #4,975 of 4,157,543 US inventors in our database (top 0.12%). Patent records list Christopher J. Penny in Saratoga Springs, NY, US.

Issued Patents All Time

Showing 1–25 of 167 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12482746 Early backside first power delivery network Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo 2025-11-25
12482704 Self-forming barrier for use in air gap formation Benjamin D. Briggs, Elbert E. Huang, Takeshi Nogami 2025-11-25
12400859 Metal hard mask for precise tuning of mandrels Joe Lee, Yann Mignot, Koichi Motoyama 2025-08-26
12243819 Single-mask alternating line deposition Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2025-03-04
12218003 Selective ILD deposition for fully aligned via with airgap Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha 2025-02-04
12156486 Horizontal RRAM device and architecture for variability reduction Timothy Mathew Philip, Nicholas Anthony Lanzillo, Youngseok Kim, Lawrence A. Clevenger 2024-11-26 $25,600,000
12106963 Self aligned pattern formation post spacer etchback in tight pitch configurations Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy +2 more 2024-10-01 $10,915,000
11990410 Top via interconnect having a line with a reduced bottom dimension Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2024-05-21 $15,464,000
11961759 Interconnects having spacers for improved top via critical dimension and overlay tolerance Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2024-04-16 $17,011,000
11955424 Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Michael Rizzolo 2024-04-09
11894265 Top via with damascene line and via Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2024-02-06 $12,408,000
11876023 Conformal film thickness determination using angled geometric features and vertices tracking Marc A. Bergendahl, James J. Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry 2024-01-16 $9,068,000
11869808 Top via process with damascene metal Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2024-01-09 $9,963,000
11854884 Fully aligned top vias Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Robert R. Robison, Lawrence A. Clevenger 2023-12-26 $6,691,000
11823998 Top via with next level line selective growth Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2023-11-21 $7,457,000
11804406 Top via cut fill process for line extension reduction Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2023-10-31 $8,788,000
11791258 Conductive lines with subtractive cuts Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2023-10-17 $7,011,000
11735524 Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo 2023-08-22 $5,113,000
11676854 Selective ILD deposition for fully aligned via with airgap Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha 2023-06-13 $11,668,000
11670542 Stepped top via for via resistance reduction Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2023-06-06 $14,513,000
11670510 Self aligned pattern formation post spacer etchback in tight pitch configurations Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy +2 more 2023-06-06 $11,771,000
11646221 Self-aligned pattern formation for a semiconductor device Sean D. Burns, Lawrence A. Clevenger, Nelson Felix, Sivananda K. Kanakasabapathy, Nicole Saulnier 2023-05-09 $3,203,000
11621189 Barrier-less prefilled via formation Nicholas Anthony Lanzillo, Hosadurga Shobha, Junli Wang, Lawrence A. Clevenger, Robert R. Robison +1 more 2023-04-04 $5,091,000
11600565 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2023-03-07 $13,230,000
11587830 Self-forming barrier for use in air gap formation Benjamin D. Briggs, Elbert E. Huang, Takeshi Nogami 2023-02-21 $10,931,000