Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12356711 | Late gate extension | Ruilong Xie, Jay William Strane, Hemanth Jagannathan, Brent A. Anderson | 2025-07-08 |
| 12249643 | Stacked planar field effect transistors with 2D material channels | Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene | 2025-03-11 |
| 12243770 | Hard mask removal without damaging top epitaxial layer | Chanro Park, Yann Mignot, Daniel J. Vincent, Su Chen Fan, Hsueh-Chung Chen | 2025-03-04 |
| 12136656 | Semiconductor structure having two-dimensional channel | Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Kangguo Cheng | 2024-11-05 |
| 12009422 | Self aligned top contact for vertical transistor | Choonghyun Lee, Chanro Park, Alexander Reznicek | 2024-06-11 |
| 11916013 | Via interconnects including super vias | Yann Mignot, Eric R. Miller, Chanro Park | 2024-02-27 |
| 11908923 | Low-resistance top contact on VTFET | Su Chen Fan, Hari Prasad Amanapu, Hemanth Jagannathan | 2024-02-20 |
| 11901440 | Sacrificial fin for self-aligned contact rail formation | Yann Mignot, Su Chen Fan, Brent A. Anderson, Junli Wang | 2024-02-13 |
| 11876124 | Vertical transistor having an oxygen-blocking layer | Chen Zhang, Shahab Siddiqui, Ruilong Xie | 2024-01-16 |
| 11876023 | Conformal film thickness determination using angled geometric features and vertices tracking | Marc A. Bergendahl, Christopher J. Penny, James J. Demarest, Jean Wynne, Jonathan Fry | 2024-01-16 |
| 11742350 | Metal gate N/P boundary control by active gate cut and recess | Andrew Gaul, Chanro Park, Julien Frougier, Ruilong Xie, Andrew M. Greene | 2023-08-29 |
| 11742354 | Top epitaxial layer and contact for VTFET | Ruilong Xie, Alexander Reznicek, Su Chen Fan, Heng Wu | 2023-08-29 |
| 11742246 | Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors | Ruilong Xie, Hemanth Jagannathan, Alexander Reznicek | 2023-08-29 |
| 11646358 | Sacrificial fin for contact self-alignment | Yann Mignot, Indira Seshadri, Su Chen Fan, Eric R. Miller | 2023-05-09 |
| 11646373 | Vertical field effect transistor with bottom spacer | Ruilong Xie, Jay William Strane, Hemanth Jagannathan | 2023-05-09 |
| 11495538 | Fully aligned via for interconnect | Ruilong Xie, Chih-Chao Yang, Lawrence A. Clevenger, Ashim Dutta | 2022-11-08 |
| 11476346 | Vertical transistor having an oxygen-blocking top spacer | Chen Zhang, Shahab Siddiqui, Ruilong Xie | 2022-10-18 |
| 11351811 | Optically-passive magnetic signature and identification feature with electromagnetic tamper detection | Michael Rizzolo, Marc A. Bergendahl, Christopher J. Penny | 2022-06-07 |
| 11316029 | Sacrificial fin for contact self-alignment | Yann Mignot, Indira Seshadri, Su Chen Fan, Eric R. Miller | 2022-04-26 |
| 11263059 | Load leveler | Jonathan Fry, Christopher J. Penny, Marc A. Bergendahl, Jean Wynne, James J. Demarest | 2022-03-01 |
| 11244861 | Method and structure for forming fully-aligned via | Ruilong Xie, Chih-Chao Yang, Huai Huang | 2022-02-08 |
| 11239165 | Method of forming an interconnect structure with enhanced corner connection | Ruilong Xie, Kangguo Cheng, Chih-Chao Yang | 2022-02-01 |
| 11217692 | Vertical field effect transistor with bottom spacer | Ruilong Xie, Jay William Strane, Hemanth Jagannathan | 2022-01-04 |
| 11211291 | Via formation with robust hardmask removal | Ruilong Xie, Kangguo Cheng, Chih-Chao Yang | 2021-12-28 |
| 11205723 | Selective source/drain recess for improved performance, isolation, and scaling | Ardasheir Rahman, Brent A. Anderson, Junli Wang, Stuart A. Sieg | 2021-12-21 |