| 12426338 |
Buried power rail with robust connection to a wrap around contact |
Ruilong Xie, Kangguo Cheng, Julien Frougier |
2025-09-23 |
|
| 12419080 |
Semiconductor structure with wrapped-around backside contact |
Ruilong Xie, Min Gyu Sung, Kangguo Cheng, Julien Frougier |
2025-09-16 |
|
| 12417944 |
Formation of trench silicide source or drain contacts without gate damage |
Andrew M. Greene, Ruilong Xie, Laertis Economikos, Veeraraghavan S. Basker, Hui Zang |
2025-09-16 |
|
| 12406920 |
Top via interconnect with airgap |
Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang |
2025-09-02 |
|
| 12402329 |
Top via containing random-access memory cross-bar array |
Koichi Motoyama, Hsueh-Chung Chen, Kenneth Chun Kuen Cheng, Chih-Chao Yang |
2025-08-26 |
|
| 12400912 |
Dual-damascene fav interconnects with dielectric plug |
Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang |
2025-08-26 |
|
| 12396225 |
Method to release nano sheet after nano sheet fin recess |
Kangguo Cheng, Ruilong Xie, Juntao Li, Choonghyun Lee |
2025-08-19 |
|
| 12389609 |
Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers |
Julien Frougier, Ruilong Xie, Kangguo Cheng, Heng Wu, Min Gyu Sung |
2025-08-12 |
|
| 12389813 |
Resistive switching memory cell |
Kangguo Cheng, Julien Frougier, Ruilong Xie |
2025-08-12 |
|
| 12382665 |
Increased gate length at given footprint for nanosheet device |
Ruilong Xie, Julien Frougier, Kangguo Cheng |
2025-08-05 |
|
| 12382662 |
Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors |
Julien Frougier, Ruilong Xie, Kangguo Cheng, Andrew Gaul |
2025-08-05 |
|
| 12382708 |
Vertical stacked nanosheet CMOS transistors with different work function metals |
Kangguo Cheng, Juntao Li, Ruilong Xie |
2025-08-05 |
|
| 12369494 |
MRAM top electrode structure with liner layer |
Hsueh-Chung Chen, Koichi Motoyama, Yann Mignot, Chih-Chao Yang |
2025-07-22 |
|
| 12362004 |
Scaled 2T DRAM |
Min Gyu Sung, Julien Frougier, Ruilong Xie, Juntao Li |
2025-07-15 |
|
| 12356638 |
Metal-insulator-metal capacitor structure with enlarged capacitor area |
Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang |
2025-07-08 |
|
| 12341100 |
Copper interconnects with self-aligned hourglass-shaped metal cap |
Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang |
2025-06-24 |
|
| 12336279 |
Fin stack including tensile-strained and compressively strained fin portions |
Kangguo Cheng, Julien Frougier, Ruilong Xie |
2025-06-17 |
|
| 12328916 |
CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation |
Julien Frougier, Ruilong Xie, Kangguo Cheng, Oleg Gluschenkov |
2025-06-10 |
|
| 12324234 |
Fork sheet device with better electrostatic control |
Ruilong Xie, Kangguo Cheng, Julien Frougier |
2025-06-03 |
|
| 12324197 |
Spin-based gate-all-around transistors |
Julien Frougier, Kangguo Cheng, Ruilong Xie, Andrew Gaul, Min Gyu Sung |
2025-06-03 |
|
| 12315807 |
Reducing copper line resistance |
Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang |
2025-05-27 |
|
| 12317514 |
Resistive random-access memory structures with stacked transistors |
Min Gyu Sung, Kangguo Cheng, Julien Frougier, Ruilong Xie, Soon-Cheon Seo |
2025-05-27 |
|
| 12310064 |
Isolation pillar structures for stacked device structures |
Ruilong Xie, Julien Frougier, Kangguo Cheng, Min Gyu Sung |
2025-05-20 |
|
| 12310061 |
Nanosheet transistor devices with different active channel widths |
Ruilong Xie, Julien Frougier, Kangguo Cheng, Cheng Chi, Jinning Liu |
2025-05-20 |
|
| 12261056 |
Top via patterning using metal as hard mask and via conductor |
Nicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger |
2025-03-25 |
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