Issued Patents All Time
Showing 1–25 of 542 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424539 | Local enlarged via-to-backside power rail | Ruilong Xie, Albert M. Chu, Carl Radens | 2025-09-23 |
| 12424591 | Method and structure of forming independent contact for staggered CFET | Ruilong Xie, Albert M. Chu, Albert M. Young, Junli Wang, Ravikumar Ramachandran | 2025-09-23 |
| 12419024 | High density static random-access memory | Ruilong Xie, Albert M. Chu, Carl Radens | 2025-09-16 |
| 12419079 | Field effect transistor with backside source/drain | Ruilong Xie, Lawrence A. Clevenger, Kisik Choi, Su Chen Fan, Shogo Mochizuki +1 more | 2025-09-16 |
| 12417979 | Pass-through wiring in notched interconnect | Nicholas Anthony Lanzillo, Albert M. Chu, Ruilong Xie, Reinaldo Vega, Lawrence A. Clevenger | 2025-09-16 |
| 12412830 | Semiconductor device with power via | Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega +2 more | 2025-09-09 |
| 12412833 | TopVia interconnect with enlarged via top | Lawrence A. Clevenger, Chen Zhang, Nicholas Anthony Lanzillo | 2025-09-09 |
| 12400960 | Vertical-transport field-effect transistor with backside gate contact | Albert M. Chu, Ruilong Xie, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Reinaldo Vega | 2025-08-26 |
| 12389582 | High density stacked vertical transistor static random access memory structure | Albert M. Chu, Junli Wang, Hemanth Jagannathan | 2025-08-12 |
| 12364004 | Dummy fin contact in vertically stacked transistors | Joshua M. Rubin, Chen Zhang, Tenko Yamashita | 2025-07-15 |
| 12356711 | Late gate extension | Ruilong Xie, Christopher J. Waskiewicz, Jay William Strane, Hemanth Jagannathan | 2025-07-08 |
| 12356685 | Looped long channel field-effect transistor | Ruilong Xie, Ardasheir Rahman, Hemanth Jagannathan, Robert R. Robison, Heng Wu | 2025-07-08 |
| 12356709 | Vertical field-effect transistor with isolation pillars | Ruilong Xie | 2025-07-08 |
| 12349458 | Staggered stacked circuits with increased effective width | Junli Wang, Albert M. Chu | 2025-07-01 |
| 12342578 | Stacked layer memory suitable for SRAM and having a long cell | Albert M. Chu, Ruilong Xie, Junli Wang, Carl Radens | 2025-06-24 |
| 12328859 | Stacked FET SRAM | Ruilong Xie, Carl Radens, Albert M. Chu, Junli Wang, Julien Frougier +1 more | 2025-06-10 |
| 12322652 | Local interconnect for cross coupling | Heng Wu, Ruilong Xie, Albert M. Chu, Albert M. Young, Junli Wang | 2025-06-03 |
| 12268016 | Buried power rail formation for vertical field effect transistors | Ruilong Xie, Junli Wang, Chen Zhang, Heng Wu, Alexander Reznicek | 2025-04-01 |
| 12268031 | Backside power rails and power distribution network for density scaling | Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert M. Chu +6 more | 2025-04-01 |
| 12268026 | High aspect ratio contact structure with multiple metal stacks | Junli Wang, Terence B. Hook, Indira Seshadri, Albert M. Young, Stuart A. Sieg +2 more | 2025-04-01 |
| 12243819 | Single-mask alternating line deposition | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2025-03-04 |
| 12142525 | Self-aligning spacer tight pitch via | Lawrence A. Clevenger, Nicholas Anthony Lanzillo | 2024-11-12 |
| 12136655 | Backside electrical contacts to buried power rails | Ruilong Xie, Albert M. Young, Kangguo Cheng, Julien Frougier, Balasubramanian Pranatharthiharan +2 more | 2024-11-05 |
| RE50181 | Isolation region fabrication for replacement gate processing | Edward J. Nowak | 2024-10-22 |
| 12057371 | Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN) | Ruilong Xie, Balasubramanian Pranatharthiharan, Mukta G. Farooq | 2024-08-06 |