Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12374615 | Electronic devices with a low dielectric constant | Hsueh-Chung Chen, Su Chen Fan, Dechao Guo, Carl Radens | 2025-07-29 |
| 12310100 | Dielectric reflow for boundary control | Jing Guo, Ekmini Anuja De Silva, Nicolas Loubet, Ruqiang Bao, Nelson Felix | 2025-05-20 |
| 12268026 | High aspect ratio contact structure with multiple metal stacks | Junli Wang, Brent A. Anderson, Terence B. Hook, Albert M. Young, Stuart A. Sieg +2 more | 2025-04-01 |
| 12107132 | Source/drain contact positioning under power rail | Ruilong Xie, Eric R. Miller, Kangguo Cheng | 2024-10-01 |
| 12021135 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Nelson Felix, Eric R. Miller | 2024-06-25 |
| 12002856 | Vertical field effect transistor with crosslink fin arrangement | Ruilong Xie, Chen Zhang, Ekmini Anuja De Silva | 2024-06-04 |
| 11916143 | Vertical transport field-effect transistor with gate patterning | Ruilong Xie, Wenyu Xu, Jing Guo, Ekmini Anuja De Silva | 2024-02-27 |
| 11855191 | Vertical FET with contact to gate above active fin | Brent A. Anderson, Junli Wang, Chen Zhang, Ruilong Xie, Joshua M. Rubin +1 more | 2023-12-26 |
| 11810828 | Transistor boundary protection using reversible crosslinking reflow | Jing Guo, Ekmini Anuja De Silva, Jingyun Zhang, Su Chen Fan | 2023-11-07 |
| 11756961 | Staggered stacked vertical crystalline semiconducting channels | Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Ekmini Anuja De Silva | 2023-09-12 |
| 11742426 | Forming crossbar and non-crossbar transistors on the same substrate | Ardasheir Rahman, Ruilong Xie, Hemanth Jagannathan | 2023-08-29 |
| 11710768 | Hybrid diffusion break with EUV gate patterning | Eric R. Miller, Andrew M. Greene, Julien Frougier, Veeraraghavan S. Basker | 2023-07-25 |
| 11695059 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Nelson Felix, Eric R. Miller | 2023-07-04 |
| 11621326 | Vertical field effect transistor with crosslink fin arrangement | Ruilong Xie, Chen Zhang, Ekmini Anuja De Silva | 2023-04-04 |
| 11569132 | Transistor structure with N/P boundary buffer | Romain Lallement, Ruqiang Bao | 2023-01-31 |
| 11515431 | Enabling residue free gap fill between nanosheets | Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Muthumanickam Sankarapandian, Nelson Felix | 2022-11-29 |
| 11500293 | Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer | Ekmini Anuja De Silva, Jing Guo, Ashim Dutta, Nelson Felix | 2022-11-15 |
| 11276767 | Additive core subtractive liner for metal cut etch processes | Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath +1 more | 2022-03-15 |
| 11251182 | Staggered stacked vertical crystalline semiconducting channels | Tsung-Sheng Kang, Tao Li, Ardasheir Rahman, Praveen Joseph, Ekmini Anuja De Silva | 2022-02-15 |
| 11245027 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Nelson Felix, Eric R. Miller | 2022-02-08 |
| 11152489 | Additive core subtractive liner for metal cut etch processes | Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath +1 more | 2021-10-19 |
| 11075281 | Additive core subtractive liner for metal cut etch processes | Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath +1 more | 2021-07-27 |
| 11075081 | Semiconductor device with multiple threshold voltages | Praveen Joseph, Ekmini Anuja De Silva | 2021-07-27 |
| 11043494 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie +2 more | 2021-06-22 |
| 10985025 | Fin cut profile using fin base liner | Eric R. Miller, Stuart A. Sieg, Yann Mignot, Christopher J. Waskiewicz | 2021-04-20 |