Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
SS

Stuart A. Sieg — 69 Patents

IBM: 61 patents #1,287 of 70,183Top 2%
TETessera: 5 patents #92 of 271Top 35%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
ASAdeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
Albany, NY: #16 of 790 inventorsTop 3%
New York: #1,108 of 115,490 inventorsTop 1%
Overall (All Time): #29,979 of 4,157,543Top 1%
69 Patents All Time
Stuart A. Sieg has been granted 69 US patents while listed as an inventor at IBM. The first was granted in 2012 and the most recent in October 2025. Stuart A. Sieg ranks #29,979 of 4,157,543 US inventors in our database (top 0.72%). Patent records list Stuart A. Sieg in Albany, NY, US.

Issued Patents All Time

Showing 1–25 of 69 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12444653 Buried power rail at tight cell-to-cell space Ruinan Xie, Somit Ghosh, Ki-Hyouk Choi, Kevin S. Petrarca 2025-10-14
12406930 Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure Ruilong Xie, Kevin S. Petrarca, Eric R. Miller 2025-09-02
12322601 Alternating hardmasks for tight-pitch line formation Sean D. Burns, Nelson Felix, Chi-Chun Liu, Yann Mignot 2025-06-03
12324236 Bottom contact for stacked GAA FET Indira Seshadri, Su Chen Fan 2025-06-03
12268026 High aspect ratio contact structure with multiple metal stacks Junli Wang, Brent A. Anderson, Terence B. Hook, Indira Seshadri, Albert M. Young +2 more 2025-04-01
12148617 Structure and method to pattern pitch lines Chanro Park, Chi-Chun Liu, Yann Mignot, Koichi Motoyama, Hsueh-Chung Chen 2024-11-19 $17,641,000
RE50174 Structure and process to tuck fin tips self-aligned to gates Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie +2 more 2024-10-15
12080559 Using a same mask for direct print and self-aligned double patterning of nanosheets Daniel James Dechene, Eric R. Miller 2024-09-03 $28,105,000
11990412 Buried power rails located in a base layer including first, second, and third etch stop layers Ruilong Xie, Somnath Ghosh, Kisik Choi, Rishikesh Krishnan, Alexander Reznicek 2024-05-21 $15,464,000
11610780 Alternating hardmasks for tight-pitch line formation Sean D. Burns, Nelson Felix, Chi-Chun Liu, Yann Mignot 2023-03-21 $8,142,000
11257681 Using a same mask for direct print and self-aligned double patterning of nanosheets Daniel James Dechene, Eric R. Miller 2022-02-22 $13,349,000
11205723 Selective source/drain recess for improved performance, isolation, and scaling Ardasheir Rahman, Brent A. Anderson, Junli Wang, Christopher J. Waskiewicz 2021-12-21 $5,237,000
11183389 Fin field effect transistor devices with self-aligned gates Wenyu Xu, Ruilong Xie, John R. Sporre 2021-11-23 $2,653,000
11171002 Alternating hardmasks for tight-pitch line formation John C. Arnold, Anuja E. DeSilva, Nelson Felix, Chi-Chun Liu, Yann Mignot 2021-11-09 $17,544,000
11121024 Tunable hardmask for overlayer metrology contrast Ekmini Anuja De Silva, Nelson Felix, Indira Seshadri 2021-09-14 $2,674,000
11031248 Alternating hardmasks for tight-pitch line formation Sean D. Burns, Nelson Felix, Chi-Chun Liu, Yann Mignot 2021-06-08 $25,375,000
10985025 Fin cut profile using fin base liner Eric R. Miller, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz 2021-04-20 $5,008,000
10943911 Vertical transport devices with greater density through modified well shapes Brent A. Anderson, Junli Wang 2021-03-09 $4,710,000
10832919 Measuring and modeling material planarization performance Romain Lallement 2020-11-10 $848,000
10811508 Vertical transistors having multiple gate thicknesses for optimizing performance and device density Brent A. Anderson, Fee Li Lie, Junli Wang 2020-10-20 $3,651,000
10811507 Vertical transistors having multiple gate thicknesses for optimizing performance and device density Brent A. Anderson, Fee Li Lie, Junli Wang 2020-10-20 $3,651,000
10741452 Controlling fin hardmask cut profile using a sacrificial epitaxial structure Eric R. Miller, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz 2020-08-11 $2,122,000
10734372 Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows Brent A. Anderson, Junli Wang 2020-08-04 $3,150,000
10665715 Controlling gate length of vertical transistors Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva 2020-05-26 $2,933,000
10642950 Verifying planarization performance using electrical measures Romain Lallement 2020-05-05 $3,712,000