Issued Patents All Time
Showing 25 most recent of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406930 | Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure | Ruilong Xie, Stuart A. Sieg, Kevin S. Petrarca | 2025-09-02 |
| 12402403 | Air gap spacer for metal gates | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2025-08-26 |
| 12349475 | Integrated circuit having vertical routing to bond pads | Christian Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne | 2025-07-01 |
| 12341099 | Semiconductor backside transistor integration with backside power delivery network | Ruilong Xie, Daniel C. Edelstein, Rajiv V. Joshi, Ravikumar Ramachandran | 2025-06-24 |
| 12327798 | Physical unclonable function | Kangguo Cheng, Fee Li Lie, Gauri Karve, Marc A. Bergendahl, John R. Sporre | 2025-06-10 |
| 12305310 | Indium electroplating on physical vapor deposition tantalum | Michael J. Rondon, Jon Sigurdson | 2025-05-20 |
| 12261186 | Mosaic focal plane array | David J. Gulbransen, Sean P. Kilcoyne, Matthew D. Chambers, Eric J. Beuville, Andrew E. Gin +1 more | 2025-03-25 |
| 12166110 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2024-12-10 |
| 12148721 | Iterative formation of damascene interconnects | Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon | 2024-11-19 |
| 12107132 | Source/drain contact positioning under power rail | Ruilong Xie, Indira Seshadri, Kangguo Cheng | 2024-10-01 |
| 12080559 | Using a same mask for direct print and self-aligned double patterning of nanosheets | Stuart A. Sieg, Daniel James Dechene | 2024-09-03 |
| 12021135 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Indira Seshadri, Nelson Felix | 2024-06-25 |
| 12002805 | Local vertical interconnects for monolithic stack transistors | Heng Wu, Ruilong Xie, Chen Zhang | 2024-06-04 |
| 11973125 | Self-aligned uniform bottom spacers for VTFETS | Ruilong Xie, Hemanth Jagannathan, Jay William Strane | 2024-04-30 |
| 11916013 | Via interconnects including super vias | Yann Mignot, Christopher J. Waskiewicz, Chanro Park | 2024-02-27 |
| 11869937 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |
| 11869936 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |
| 11837623 | Integrated circuit having vertical routing to bond pads | Christian Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne | 2023-12-05 |
| 11791398 | Nano multilayer carbon-rich low-k spacer | Donald F. Canaperi, Richard A. Conti, Thomas J. Haigh, Jr., Son V. Nguyen | 2023-10-17 |
| 11753736 | Indium electroplating on physical vapor deposition tantalum | Michael J. Rondon, Jon Sigurdson | 2023-09-12 |
| 11710756 | Integrating optical elements with electro-optical sensors via direct-bond hybridization | Jamal I. Mustafa, Robert C. Anderson, John L. Vampola, Sean P. Kilcoyne, George Grama | 2023-07-25 |
| 11710768 | Hybrid diffusion break with EUV gate patterning | Indira Seshadri, Andrew M. Greene, Julien Frougier, Veeraraghavan S. Basker | 2023-07-25 |
| 11695059 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Indira Seshadri, Nelson Felix | 2023-07-04 |
| 11673766 | Elevator analytics facilitating passenger destination prediction and resource optimization | Gauri Karve, Tara Astigarraga, Kangguo Cheng, Fee Li Lie, Sean Teehan +1 more | 2023-06-13 |
| 11652161 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2023-05-16 |