RR

Ravikumar Ramachandran

IBM: 94 patents #629 of 70,183Top 1%
Infineon Technologies Ag: 18 patents #563 of 7,486Top 8%
Globalfoundries: 11 patents #330 of 4,424Top 8%
SA Siemens Aktiengesellschaft: 7 patents #1,726 of 22,248Top 8%
FS Freeescale Semiconductor: 1 patents #2,021 of 3,767Top 55%
KT Kabushiki Kaisha Toshiba: 1 patents #13,537 of 21,451Top 65%
Overall (All Time): #11,686 of 4,157,543Top 1%
111
Patents All Time

Issued Patents All Time

Showing 25 most recent of 111 patents

Patent #TitleCo-InventorsDate
12424591 Method and structure of forming independent contact for staggered CFET Ruilong Xie, Albert M. Chu, Albert M. Young, Brent A. Anderson, Junli Wang 2025-09-23
12412829 Method and structure of forming sidewall contact for stacked FET Ruilong Xie, Julien Frougier, Su Chen Fan, Oleg Gluschenkov 2025-09-09
12341099 Semiconductor backside transistor integration with backside power delivery network Ruilong Xie, Daniel C. Edelstein, Rajiv V. Joshi, Eric R. Miller 2025-06-24
12328859 Stacked FET SRAM Ruilong Xie, Carl Radens, Albert M. Chu, Brent A. Anderson, Junli Wang +1 more 2025-06-10
11961895 Gate stacks with multiple high-κ dielectric layers Ruqiang Bao, Barry P. Linder, Shahab Siddiqui, Elnatan Mataev 2024-04-16
11935929 High aspect ratio shared contacts Ruilong Xie, Julien Frougier, Su Chen Fan, Nicolas Loubet 2024-03-19
11895818 Stacked FET SRAM Ruilong Xie, Carl Radens, Junli Wang, Julien Frougier, Dechao Guo 2024-02-06
11139299 FinFET based ZRAM with convex channel region Reinaldo Vega 2021-10-05
10832971 Fabricating tapered semiconductor devices Rajasekhar Venigalla, Albert M. Chu, Alan C. Thomas, Kafai Lai 2020-11-10
10693005 Reliable gate contacts over active areas Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na 2020-06-23
10573646 Preserving channel strain in fin cuts Andrew M. Greene, Dechao Guo, Rajasekhar Venigalla 2020-02-25
10424574 Standard cell architecture with at least one gate contact over an active area Albert M. Chu, Myung-Hee Na 2019-09-24
10424576 Standard cell architecture with at least one gate contact over an active area Albert M. Chu, Myung-Hee Na 2019-09-24
10403628 Finfet based ZRAM with convex channel region Reinaldo Vega 2019-09-03
10381480 Reliable gate contacts over active areas Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na 2019-08-13
10256238 Preserving channel strain in fin cuts Andrew M. Greene, Dechao Guo, Rajasekhar Venigalla 2019-04-09
10242980 Semiconductor fin isolation by a well trapping fin portion Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Huiling Shang, Reinaldo Vega 2019-03-26
10242918 Shallow trench isolation structures and contact patterning Andrew M. Greene, Rajasekhar Venigalla 2019-03-26
10177154 Structure and method to prevent EPI short between trenches in FinFET eDRAM Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz +5 more 2019-01-08
10177039 Shallow trench isolation structures and contact patterning Andrew M. Greene, Rajasekhar Venigalla 2019-01-08
10128239 Preserving channel strain in fin cuts Andrew M. Greene, Dechao Guo, Rajasekhar Venigalla 2018-11-13
10083865 Partial spacer for increasing self aligned contact process margins Emre Alptekin, Viraj Y. Sardesai, Reinaldo Vega 2018-09-25
10074562 Self aligned contact structure Rosa A. Orozco-Teran, John A. Fitzsimmons, Russell H. Arndt, David L. Rath 2018-09-11
9985104 Contact first replacement metal gate Emre Alptekin, Viraj Y. Sardesai 2018-05-29
9929047 Partial spacer for increasing self aligned contact process margins Emre Alptekin, Viraj Y. Sardesai, Reinaldo Vega 2018-03-27