Issued Patents All Time
Showing 1–25 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424539 | Local enlarged via-to-backside power rail | Ruilong Xie, Carl Radens, Brent A. Anderson | 2025-09-23 |
| 12424591 | Method and structure of forming independent contact for staggered CFET | Ruilong Xie, Albert M. Young, Brent A. Anderson, Junli Wang, Ravikumar Ramachandran | 2025-09-23 |
| 12419024 | High density static random-access memory | Brent A. Anderson, Ruilong Xie, Carl Radens | 2025-09-16 |
| 12417979 | Pass-through wiring in notched interconnect | Nicholas Anthony Lanzillo, Ruilong Xie, Reinaldo Vega, Lawrence A. Clevenger, Brent A. Anderson | 2025-09-16 |
| 12412830 | Semiconductor device with power via | Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega +2 more | 2025-09-09 |
| 12400960 | Vertical-transport field-effect transistor with backside gate contact | Brent A. Anderson, Ruilong Xie, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Reinaldo Vega | 2025-08-26 |
| 12389582 | High density stacked vertical transistor static random access memory structure | Brent A. Anderson, Junli Wang, Hemanth Jagannathan | 2025-08-12 |
| 12363965 | Stacked transistor layout for improved cell height scaling | Ruilong Xie, Nicholas Anthony Lanzillo, Daniel James Dechene, Eric Miller, Lawrence A. Clevenger | 2025-07-15 |
| 12362278 | Transistors with dual power and signal lines | Tao Li, Ruilong Xie, David Wolpert | 2025-07-15 |
| 12349458 | Staggered stacked circuits with increased effective width | Brent A. Anderson, Junli Wang | 2025-07-01 |
| 12342578 | Stacked layer memory suitable for SRAM and having a long cell | Brent A. Anderson, Ruilong Xie, Junli Wang, Carl Radens | 2025-06-24 |
| 12328859 | Stacked FET SRAM | Ruilong Xie, Carl Radens, Brent A. Anderson, Junli Wang, Julien Frougier +1 more | 2025-06-10 |
| 12322652 | Local interconnect for cross coupling | Heng Wu, Ruilong Xie, Albert M. Young, Junli Wang, Brent A. Anderson | 2025-06-03 |
| 12295133 | SRAM with backside cross-couple | Ruilong Xie, Carl Radens, Kisik Choi | 2025-05-06 |
| 12278184 | Vertically-stacked field effect transistor cell | Junli Wang, Albert M. Young, Dechao Guo | 2025-04-15 |
| 12268031 | Backside power rails and power distribution network for density scaling | Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert M. Young +6 more | 2025-04-01 |
| 12142656 | Staggered stacked semiconductor devices | Junli Wang, Albert M. Young, Vidhi Zalani, Dechao Guo | 2024-11-12 |
| 12001772 | Ultra-short-height standard cell architecture | Junli Wang, Brent A. Anderson | 2024-06-04 |
| 11658116 | Interconnects on multiple sides of a semiconductor structure | Junli Wang, Dechao Guo, Brent A. Anderson | 2023-05-23 |
| 11355401 | Field effect transistor | Effendi Leobandung, Veeraraghavan S. Basker, Junli Wang | 2022-06-07 |
| 11031296 | 3D vertical FET with top and bottom gate contacts | Brent A. Anderson | 2021-06-08 |
| 10832971 | Fabricating tapered semiconductor devices | Rajasekhar Venigalla, Ravikumar Ramachandran, Alan C. Thomas, Kafai Lai | 2020-11-10 |
| 10755969 | Multi-patterning techniques for fabricating an array of metal lines with different widths | Kafai Lai, Lawrence A. Clevenger | 2020-08-25 |
| 10755017 | Cell placement in a circuit with shared inputs and outputs | Brent A. Anderson, Laura R. Darden, Alexander J. Suess | 2020-08-25 |
| 10742218 | Vertical transport logic circuit cell with shared pitch | Brent A. Anderson | 2020-08-11 |