| 12506080 |
Reduced capacitance between power via bar and gates |
Ruinan Xie, Ki-Hyouk Choi, Reinaldo Vega, Nicholas Anthony Lanzillo, Lawrence A. Clevenger |
2025-12-23 |
|
| 12500144 |
Backside self aligned skip via |
Ruinan Xie, Biswanath Senapati, David Wolpert, Nicholas Anthony Lanzillo, Lawrence A. Clevenger +3 more |
2025-12-16 |
|
| 12490465 |
Stacked field effect transistor |
Brent A. Anderson, Ruinan Xie, Albert Young |
2025-12-02 |
|
| 12490507 |
Different dimensions across active region for stronger via to backside power rail |
Ruinan Xie, Carl Radens, Brent A. Anderson |
2025-12-02 |
|
| 12484248 |
Source/drain contact at tight cell boundary |
Ruinan Xie, Nicholas Anthony Lanzillo, Brent A. Anderson, Reinaldo Vega, Lawrence A. Clevenger |
2025-11-25 |
|
| 12484265 |
Subtractive source drain contact for stacked devices |
Heng Wu, Junli Wang, Ruinan Xie, Albert Young, Brent A. Anderson +1 more |
2025-11-25 |
|
| 12463128 |
Interconnect structures with vias having vertical and horizontal sections |
Ruinan Xie, Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo |
2025-11-04 |
|
| 12463130 |
Wrap around metal via structure |
Reinaldo Vega, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Ruinan Xie, Brent A. Anderson |
2025-11-04 |
|
| 12457793 |
Vertical transport field effect transistor (VTFET) with backside wraparound contact |
Ruinan Xie, Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Reinaldo Vega |
2025-10-28 |
|
| 12446290 |
Asymmetric gate extension in stacked FET |
Ruinan Xie, Brent A. Anderson, Junli Wang, Jay William Strane |
2025-10-14 |
|
| 12439660 |
Vertical transistor with reduced cell height |
Brent A. Anderson, Ruinan Xie, Hemanth Jagannathan, Junli Wang |
2025-10-07 |
|
| 12424539 |
Local enlarged via-to-backside power rail |
Ruilong Xie, Carl Radens, Brent A. Anderson |
2025-09-23 |
|
| 12424591 |
Method and structure of forming independent contact for staggered CFET |
Ruilong Xie, Albert M. Young, Brent A. Anderson, Junli Wang, Ravikumar Ramachandran |
2025-09-23 |
|
| 12419024 |
High density static random-access memory |
Brent A. Anderson, Ruilong Xie, Carl Radens |
2025-09-16 |
|
| 12417979 |
Pass-through wiring in notched interconnect |
Nicholas Anthony Lanzillo, Ruilong Xie, Reinaldo Vega, Lawrence A. Clevenger, Brent A. Anderson |
2025-09-16 |
|
| 12412830 |
Semiconductor device with power via |
Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega +2 more |
2025-09-09 |
|
| 12400960 |
Vertical-transport field-effect transistor with backside gate contact |
Brent A. Anderson, Ruilong Xie, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Reinaldo Vega |
2025-08-26 |
|
| 12389582 |
High density stacked vertical transistor static random access memory structure |
Brent A. Anderson, Junli Wang, Hemanth Jagannathan |
2025-08-12 |
|
| 12363965 |
Stacked transistor layout for improved cell height scaling |
Ruilong Xie, Nicholas Anthony Lanzillo, Daniel James Dechene, Eric Miller, Lawrence A. Clevenger |
2025-07-15 |
|
| 12362278 |
Transistors with dual power and signal lines |
Tao Li, Ruilong Xie, David Wolpert |
2025-07-15 |
|
| 12349458 |
Staggered stacked circuits with increased effective width |
Brent A. Anderson, Junli Wang |
2025-07-01 |
|
| 12342578 |
Stacked layer memory suitable for SRAM and having a long cell |
Brent A. Anderson, Ruilong Xie, Junli Wang, Carl Radens |
2025-06-24 |
|
| 12328859 |
Stacked FET SRAM |
Ruilong Xie, Carl Radens, Brent A. Anderson, Junli Wang, Julien Frougier +1 more |
2025-06-10 |
|
| 12322652 |
Local interconnect for cross coupling |
Heng Wu, Ruilong Xie, Albert M. Young, Junli Wang, Brent A. Anderson |
2025-06-03 |
|
| 12295133 |
SRAM with backside cross-couple |
Ruilong Xie, Carl Radens, Kisik Choi |
2025-05-06 |
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