Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8519772 | Alternate power gating enablement | Daryl M. Seitzer, Rohit Shetty, Douglas W. Stout | 2013-08-27 |
| 7873921 | Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal | Wagdi W. Abadeer, Jeffrey S. Brown, John A. Fifield | 2011-01-18 |
| 7847605 | Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal | Wagdi W. Abadeer, Jeffrey S. Brown, John A. Fifield | 2010-12-07 |
| 7839206 | Design structure for low voltage applications in an integrated circuit | Wagdi W. Abadeer | 2010-11-23 |
| 7818694 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Michael S. Gray, Jason D. Hibbeler, Daniel N. Maynard +2 more | 2010-10-19 |
| 7646573 | Method for improved triggering and oscillation suppression of ESD clamping devices | Robert J. Gauthier, Jr., Junjun Li, Thomas W. Wyckoff | 2010-01-12 |
| 7573300 | Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same | Wagdi W. Abadeer, George M. Braceras, John A. Fifield, Harold Pilo, Daryl M. Seitzer | 2009-08-11 |
| 7503020 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Michael S. Gray, Jason D. Hibbeler, Daniel N. Maynard +2 more | 2009-03-10 |
| 7471114 | Design structure for a current control mechanism for power networks and dynamic logic keeper circuits | Wagdi W. Abadeer, George M. Braceras, John A. Fifield, Harold Pilo, Daryl M. Seitzer | 2008-12-30 |
| 7466171 | Voltage detection circuit and circuit for generating a trigger flag signal | Wagdi W. Abadeer, Jeffrey S. Brown, John A. Fifield | 2008-12-16 |
| 7397641 | Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices | Robert J. Gauthier, Jr., Junjun Li, Thomas W. Wyckoff | 2008-07-08 |
| 6760240 | CAM cell with interdigitated search and bit lines | Robert E. Busch, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter | 2004-07-06 |
| 6760881 | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) | Kevin A. Batson, Robert E. Busch, Ezra D. B. Hall | 2004-07-06 |
| 6671218 | System and method for hiding refresh cycles in a dynamic type content addressable memory | Paul Gutwin, Jonathan B. Ashbrook, Michael Bogaczyk, Ezra D. B. Hall, Daryl M. Seitzer | 2003-12-30 |
| 6487101 | Use of search lines as global bitlines in a cam design | Jonathan B. Ashbrook, Robert E. Busch, Daryl M. Seitzer | 2002-11-26 |
| 6421784 | Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element | Daniel M. Dreps, Frank D. Ferraiolo, Kevin C. Gower, Roger P. Gregor | 2002-07-16 |
| 6285229 | Digital delay line with low insertion delay | Frank D. Ferraiolo, John A. Fifield, Teresa Thi Nguyen, Michael Sofranko | 2001-09-04 |
| 6252443 | Delay element using a delay locked loop | Jean-Marc Dortu, Frank D. Ferraiolo | 2001-06-26 |
| 6229364 | Frequency range trimming for a delay line | Jean-Marc Dortu, Christopher Miller | 2001-05-08 |
| 6127866 | Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays | John A. Fifield, Jason Rotella, Jean-Marc Dortu | 2000-10-03 |
| 6100733 | Clock latency compensation circuit for DDR timing | Jean-Marc Dortu | 2000-08-08 |
| 6025744 | Glitch free delay line multiplexing technique | Allan Robert Bertolet, Frank D. Ferraiolo, Samuel Weinstein | 2000-02-15 |
| 5777504 | Couple noise protection circuit technique | Ronald A. Piro | 1998-07-07 |
| 5389836 | Branch isolation circuit for cascode voltage switch logic | Allan Robert Bertolet, William R. Griffin, John G. Petrovick, Jr., Larry Wissel | 1995-02-14 |
| 4988896 | High speed CMOS latch without pass-gates | — | 1991-01-29 |