{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "IBM", "item": "https://www.patentleaderboard.com/company/ibm"}, {"@type": "ListItem", "position": 3, "name": "Michael S. Gray", "item": "https://www.patentleaderboard.com/inventor/fl:mi_ln:gray-18"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MG

Michael S. Gray — 25 Patents

IBM: 22 patents #4,922 of 70,183Top 8%
BLBradken Resources Pty Limited: 1 patents #17 of 38Top 45%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
ZPZenith Sintered Products: 1 patents #5 of 8Top 65%
Saint Albans, VT: #6 of 84 inventorsTop 8%
Vermont: #300 of 4,968 inventorsTop 7%
Overall (All Time): #158,593 of 4,157,543Top 4%
25 Patents All Time
Michael S. Gray has been granted 25 US patents while listed as an inventor at IBM. The first was granted in 2000 and the most recent in November 2024. Michael S. Gray ranks #158,593 of 4,157,543 US inventors in our database (top 3.8%). Patent records list Michael S. Gray in Saint Albans, VT, US.

Patents per Year

Patents granted per year, 2000 to 2024Bar chart with a peak of 3 patents in 2006.peak 32000: 1 patents20002006: 3 patents2007: 1 patents20072009: 3 patents2010: 3 patents20102011: 2 patents2012: 2 patents20122013: 2 patents2015: 1 patents20152018: 1 patents2021: 2 patents20212022: 1 patents2023: 1 patents20232024: 2 patents2024

Issued Patents All Time

Showing 1–25 of 25 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12138634 Mill liner, coupling tool and method of removal of a mill liner David Joel STEWART, Terry Alexander SHORE 2024-11-12
12112114 Hierarchical color decomposition of library cells with boundary-aware color selection David Wolpert, Leon Sigal, Mitchell R. DeHond 2024-10-08 $24,159,000
11822867 Hierarchical color decomposition of process layers with shape and orientation requirements David Wolpert, Leon Sigal, Mitchell R. DeHond 2023-11-21 $7,457,000
11308257 Stacked via rivets in chip hotspots Dureseti Chidambarrao, David Wolpert, Atsushi Ogino, Matthew T. Guzowski, Steven P. Ostrander +1 more 2022-04-19 $6,872,000
11055465 Fill techniques for avoiding Boolean DRC failures during cell placement David Wolpert, Timothy A. Schell, Erwin Behnen, Robert M. Averill, III 2021-07-06 $5,313,000
10885260 Fin-based fill cell optimization David Wolpert, Timothy A. Schell, Erwin Behnen, Robert M. Averill, III 2021-01-05 $2,293,000
9971861 Selective boundary overlay insertion for hierarchical circuit design Erwin Behnen, Matthew T. Guzowski, David Wolpert 2018-05-15 $2,944,000
9158885 Reducing color conflicts in triple patterning lithography Matthew T. Guzowski, Alexander Ivrii, Lars Liebmann, Kevin W. McCullen, Gustavo E. Tellez +1 more 2015-10-13 $929,000
8555229 Parallel solving of layout optimization Xiaoping Tang, Xin Yuan 2013-10-08 $7,754,000
8448124 Post timing layout modification for performance Uwe Fassnacht, Veit Gernhoefer, Joachim Keinert 2013-05-21 $6,083,000
8302062 Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization Xiaoping Tang, Xin Yuan 2012-10-30
8296706 Handling two-dimensional constraints in integrated circuit layout Xiaoping Tang, Xin Yuan 2012-10-23 $6,526,000
7895562 Adaptive weighting method for layout optimization with multiple priorities Matthew T. Guzowski, Kevin W. McCullen, Xiaoping Tang, Robert F. Walker, Xin Yuan 2011-02-22 $3,876,000
7865848 Layout optimization using parameterized cells Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker +1 more 2011-01-04 $2,931,000
7818694 IC layout optimization to improve yield Robert J. Allen, Faye D. Baker, Albert M. Chu, Jason D. Hibbeler, Daniel N. Maynard +2 more 2010-10-19 $3,706,000
7761818 Obtaining a feasible integer solution in a hierarchical circuit layout optimization Xiaoping Tang, Xin Yuan 2010-07-20 $3,139,000
7735042 Context aware sub-circuit layout modification Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker, Xin Yuan 2010-06-08 $3,517,000
7503020 IC layout optimization to improve yield Robert J. Allen, Faye D. Baker, Albert M. Chu, Jason D. Hibbeler, Daniel N. Maynard +2 more 2009-03-10 $6,331,000
7490308 Method for implementing overlay-based modification of VLSI design layout Christopher Gonzalez, Matthew T. Guzowski, Jason D. Hibbeler, Stephen I. Runyon, Xiaoyun K. Wu 2009-02-10 $5,620,000
7484197 Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs Robert J. Allen, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +2 more 2009-01-27 $4,993,000
7260790 Integrated circuit yield enhancement using Voronoi diagrams Robert J. Allen, Jason D. Hibbeler, Mervyn Y. Tan, Robert F. Walker 2007-08-21 $7,896,000
7120887 Cloned and original circuit shape merging Henry A. Bonges, III, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker 2006-10-10 $5,276,000
7117456 Circuit area minimization using scaling Kevin W. McCullen, Gustavo E. Tellez, Robert F. Walker 2006-10-03 $4,350,000
7062729 Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization Jason D. Hibbeler, Gustavo E. Tellez, Robert F. Walker 2006-06-13 $6,535,000
6013225 Surface densification of machine components made by powder metallurgy Terry M. Cadle, Timothy E. Geiman, Joel H. Mandel 2000-01-11