Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12138634 | Mill liner, coupling tool and method of removal of a mill liner | David Joel STEWART, Terry Alexander SHORE | 2024-11-12 |
| 12112114 | Hierarchical color decomposition of library cells with boundary-aware color selection | David Wolpert, Leon Sigal, Mitchell R. DeHond | 2024-10-08 |
| 11822867 | Hierarchical color decomposition of process layers with shape and orientation requirements | David Wolpert, Leon Sigal, Mitchell R. DeHond | 2023-11-21 |
| 11308257 | Stacked via rivets in chip hotspots | Dureseti Chidambarrao, David Wolpert, Atsushi Ogino, Matthew T. Guzowski, Steven P. Ostrander +1 more | 2022-04-19 |
| 11055465 | Fill techniques for avoiding Boolean DRC failures during cell placement | David Wolpert, Timothy A. Schell, Erwin Behnen, Robert M. Averill, III | 2021-07-06 |
| 10885260 | Fin-based fill cell optimization | David Wolpert, Timothy A. Schell, Erwin Behnen, Robert M. Averill, III | 2021-01-05 |
| 9971861 | Selective boundary overlay insertion for hierarchical circuit design | Erwin Behnen, Matthew T. Guzowski, David Wolpert | 2018-05-15 |
| 9158885 | Reducing color conflicts in triple patterning lithography | Matthew T. Guzowski, Alexander Ivrii, Lars Liebmann, Kevin W. McCullen, Gustavo E. Tellez +1 more | 2015-10-13 |
| 8555229 | Parallel solving of layout optimization | Xiaoping Tang, Xin Yuan | 2013-10-08 |
| 8448124 | Post timing layout modification for performance | Uwe Fassnacht, Veit Gernhoefer, Joachim Keinert | 2013-05-21 |
| 8302062 | Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization | Xiaoping Tang, Xin Yuan | 2012-10-30 |
| 8296706 | Handling two-dimensional constraints in integrated circuit layout | Xiaoping Tang, Xin Yuan | 2012-10-23 |
| 7895562 | Adaptive weighting method for layout optimization with multiple priorities | Matthew T. Guzowski, Kevin W. McCullen, Xiaoping Tang, Robert F. Walker, Xin Yuan | 2011-02-22 |
| 7865848 | Layout optimization using parameterized cells | Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Stephen L. Runyon, Robert F. Walker +1 more | 2011-01-04 |
| 7818694 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Albert M. Chu, Jason D. Hibbeler, Daniel N. Maynard +2 more | 2010-10-19 |
| 7761818 | Obtaining a feasible integer solution in a hierarchical circuit layout optimization | Xiaoping Tang, Xin Yuan | 2010-07-20 |
| 7735042 | Context aware sub-circuit layout modification | Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker, Xin Yuan | 2010-06-08 |
| 7503020 | IC layout optimization to improve yield | Robert J. Allen, Faye D. Baker, Albert M. Chu, Jason D. Hibbeler, Daniel N. Maynard +2 more | 2009-03-10 |
| 7490308 | Method for implementing overlay-based modification of VLSI design layout | Christopher Gonzalez, Matthew T. Guzowski, Jason D. Hibbeler, Stephen I. Runyon, Xiaoyun K. Wu | 2009-02-10 |
| 7484197 | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs | Robert J. Allen, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +2 more | 2009-01-27 |
| 7260790 | Integrated circuit yield enhancement using Voronoi diagrams | Robert J. Allen, Jason D. Hibbeler, Mervyn Y. Tan, Robert F. Walker | 2007-08-21 |
| 7120887 | Cloned and original circuit shape merging | Henry A. Bonges, III, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker | 2006-10-10 |
| 7117456 | Circuit area minimization using scaling | Kevin W. McCullen, Gustavo E. Tellez, Robert F. Walker | 2006-10-03 |
| 7062729 | Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization | Jason D. Hibbeler, Gustavo E. Tellez, Robert F. Walker | 2006-06-13 |
| 6013225 | Surface densification of machine components made by powder metallurgy | Terry M. Cadle, Timothy E. Geiman, Joel H. Mandel | 2000-01-11 |