| 12500144 |
Backside self aligned skip via |
Ruinan Xie, Biswanath Senapati, David Wolpert, Nicholas Anthony Lanzillo, Lawrence A. Clevenger +3 more |
2025-12-16 |
|
| 12451412 |
Backside gate via structure using self-aligned scheme |
Tsung-Sheng Kang, Tao Li, Ruinan Xie |
2025-10-21 |
|
| 12381149 |
Cell optimization through source resistance improvement |
David Wolpert, Bharat Biyani |
2025-08-05 |
|
| 12271674 |
Generating a power delivery network based on the routing of signal wires within a circuit design |
David Wolpert, Matthew T. Guzowski, Michael H. Wood |
2025-04-08 |
|
| 12176289 |
Semiconductor device design mitigating latch-up |
David Wolpert, Terence B. Hook |
2024-12-24 |
$24,905,000 |
| 12112114 |
Hierarchical color decomposition of library cells with boundary-aware color selection |
David Wolpert, Michael S. Gray, Mitchell R. DeHond |
2024-10-08 |
$24,159,000 |
| 11916384 |
Region-based power grid generation through modification of an initial power grid based on timing analysis |
David Wolpert, Basanth Jagannathan, Michael H. Wood, James Leland, Alexander J. Suess +2 more |
2024-02-27 |
$9,833,000 |
| 11822867 |
Hierarchical color decomposition of process layers with shape and orientation requirements |
David Wolpert, Michael S. Gray, Mitchell R. DeHond |
2023-11-21 |
$7,457,000 |
| 11663391 |
Latch-up avoidance for sea-of-gates |
David Wolpert, Ryan Michael Kruse, Richard Edward Serton, Matthew S. Angyal, Terence B. Hook +1 more |
2023-05-30 |
$4,328,000 |
| 11106850 |
Flexible constraint-based logic cell placement |
David Wolpert, Timothy A. Schell, Erwin Behnen |
2021-08-31 |
$6,618,000 |
| 11074391 |
Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips |
David Kadzov, Nagashyamala R. Dhanwada, James D. Warnock |
2021-07-27 |
$4,187,000 |
| 9990454 |
Early analysis and mitigation of self-heating in design flows |
Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets +3 more |
2018-06-05 |
$4,786,000 |
| 9552455 |
Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications |
Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, James D. Warnock |
2017-01-24 |
$6,909,000 |
| 9104832 |
Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design |
John E. Barwin, Jason Chung, Amol A. Joshi, William J. Livingstone, Brian Worth +1 more |
2015-08-11 |
$2,160,000 |
| 8914765 |
Power grid generation through modification of an initial power grid based on power grid analysis |
James D. Warnock |
2014-12-16 |
$3,695,000 |
| 8354858 |
Apparatus and method for hardening latches in SOI CMOS devices |
Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more |
2013-01-15 |
$8,874,000 |
| 8117579 |
LSSD compatibility for GSD unified global clock buffers |
James D. Warnock, Wendel Dieter, David E. Lackey, William V. Huott, Louis Bernard Bushard +1 more |
2012-02-14 |
$8,403,000 |
| 7888959 |
Apparatus and method for hardening latches in SOI CMOS devices |
Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more |
2011-02-15 |
$3,434,000 |
| 7589565 |
Low-power multi-output local clock buffer |
James D. Warnock, Dieter Wendel |
2009-09-15 |
$26,046,000 |
| 7568173 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration |
Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +5 more |
2009-07-28 |
$11,761,000 |
| 7456671 |
Hierarchical scalable high resolution digital programmable delay circuit |
Charlie C. Hwang, Phillip J. Restle |
2008-11-25 |
$6,627,000 |
| 7100144 |
System and method for topology selection to minimize leakage power during synthesis |
Hans M. Jacobson, Prabhakar Kudva |
2006-08-29 |
$3,832,000 |
| 6629298 |
Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design |
Peter J. Camporese, Adam R. Jatkowski, Patrick M. Williams |
2003-09-30 |
$10,221,000 |
| 5910730 |
Digital circuit noise margin improvement |
— |
1999-06-08 |
$54,177,000 |
| 5757682 |
Parallel calculation of exponent and sticky bit during normalization |
Eric M. Schwarz, Robert M. Bunce, Hung C. Ngo |
1998-05-26 |
$6,589,000 |
