Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381149 | Cell optimization through source resistance improvement | David Wolpert, Bharat Biyani | 2025-08-05 |
| 12271674 | Generating a power delivery network based on the routing of signal wires within a circuit design | David Wolpert, Matthew T. Guzowski, Michael H. Wood | 2025-04-08 |
| 12176289 | Semiconductor device design mitigating latch-up | David Wolpert, Terence B. Hook | 2024-12-24 |
| 12112114 | Hierarchical color decomposition of library cells with boundary-aware color selection | David Wolpert, Michael S. Gray, Mitchell R. DeHond | 2024-10-08 |
| 11916384 | Region-based power grid generation through modification of an initial power grid based on timing analysis | David Wolpert, Basanth Jagannathan, Michael H. Wood, James Leland, Alexander J. Suess +2 more | 2024-02-27 |
| 11822867 | Hierarchical color decomposition of process layers with shape and orientation requirements | David Wolpert, Michael S. Gray, Mitchell R. DeHond | 2023-11-21 |
| 11663391 | Latch-up avoidance for sea-of-gates | David Wolpert, Ryan Michael Kruse, Richard Edward Serton, Matthew S. Angyal, Terence B. Hook +1 more | 2023-05-30 |
| 11106850 | Flexible constraint-based logic cell placement | David Wolpert, Timothy A. Schell, Erwin Behnen | 2021-08-31 |
| 11074391 | Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips | David Kadzov, Nagashyamala R. Dhanwada, James D. Warnock | 2021-07-27 |
| 9990454 | Early analysis and mitigation of self-heating in design flows | Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets +3 more | 2018-06-05 |
| 9552455 | Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications | Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, James D. Warnock | 2017-01-24 |
| 9104832 | Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design | John E. Barwin, Jason Chung, Amol A. Joshi, William J. Livingstone, Brian Worth +1 more | 2015-08-11 |
| 8914765 | Power grid generation through modification of an initial power grid based on power grid analysis | James D. Warnock | 2014-12-16 |
| 8354858 | Apparatus and method for hardening latches in SOI CMOS devices | Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more | 2013-01-15 |
| 8117579 | LSSD compatibility for GSD unified global clock buffers | James D. Warnock, Wendel Dieter, David E. Lackey, William V. Huott, Louis Bernard Bushard +1 more | 2012-02-14 |
| 7888959 | Apparatus and method for hardening latches in SOI CMOS devices | Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges +2 more | 2011-02-15 |
| 7589565 | Low-power multi-output local clock buffer | James D. Warnock, Dieter Wendel | 2009-09-15 |
| 7568173 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration | Veit Gernhoefer, Matthew T. Guzowski, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +5 more | 2009-07-28 |
| 7456671 | Hierarchical scalable high resolution digital programmable delay circuit | Charlie C. Hwang, Phillip J. Restle | 2008-11-25 |
| 7100144 | System and method for topology selection to minimize leakage power during synthesis | Hans M. Jacobson, Prabhakar Kudva | 2006-08-29 |
| 6629298 | Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design | Peter J. Camporese, Adam R. Jatkowski, Patrick M. Williams | 2003-09-30 |
| 5910730 | Digital circuit noise margin improvement | — | 1999-06-08 |
| 5757682 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Hung C. Ngo | 1998-05-26 |
| 5742536 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Hung C. Ngo | 1998-04-21 |
| 5742535 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Hung C. Ngo | 1998-04-21 |