Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9323875 | Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations | Peter A. Habitz, Amith Singhee, James E. Sundquist, Wangyang Zhang | 2016-04-26 |
| 9104832 | Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design | John E. Barwin, Jason Chung, William J. Livingstone, Leon Sigal, Brian Worth +1 more | 2015-08-11 |
| 8855993 | Integrated circuit design simulation matrix interpolation | Peter A. Habitz | 2014-10-07 |
| 8713502 | Methods and systems to reduce a number of simulations in a timing analysis | Nilesh C. Date, David Bruce White, William J. Wright | 2014-04-29 |
| 8656325 | Integrated circuit design method and system | John E. Barwin, Baozhen Li, Michael R. Ouellette | 2014-02-18 |
| 8413095 | Statistical single library including on chip variation for rapid timing and power analysis | John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Christopher J. Kiegle +2 more | 2013-04-02 |
| 8230382 | Model based simulation of electronic discharge and optimization methodology for design checking | Robert J. Gauthier, Jr., Bradford Lawrence Hunter, Junjun Li, Gregory J. Schroer | 2012-07-24 |
| 7533357 | Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis | Kurt A. Carlsen, Faraydon Pakbaz, Sanjay Upreti | 2009-05-12 |
| 7231335 | Method and apparatus for performing input/output floor planning on an integrated circuit design | Jerry D. Hayes, Natesan Venkateswaran, William J. Wright | 2007-06-12 |