Issued Patents All Time
Showing 25 most recent of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489540 | Integrating manufacturing feedback into integrated circuit structure design | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +4 more | 2019-11-26 |
| 9858368 | Integrating manufacturing feedback into integrated circuit structure design | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +4 more | 2018-01-02 |
| 9378328 | Modeling multi-patterning variability with statistical timing | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2016-06-28 |
| 9323875 | Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations | Amol A. Joshi, Amith Singhee, James E. Sundquist, Wangyang Zhang | 2016-04-26 |
| 9171124 | Parasitic extraction in an integrated circuit with multi-patterning requirements | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2015-10-27 |
| 9157956 | Adaptive power control using timing canonicals | Jeanne P. Bickford, Eric A. Foreman, Jeffrey G. Hemmett, Clarence R. Ogilvie, Tad J. Wilder +1 more | 2015-10-13 |
| 9104834 | Systems and methods for single cell product path delay analysis | Jeanne P. Bickford, Vikram Iyengar, Brian Worth, Jinjun Xiong | 2015-08-11 |
| 9058034 | Integrated circuit product yield optimization using the results of performance path testing | Jeanne P. Bickford, Vikram Iyengar, Jinjun Xiong | 2015-06-16 |
| 8949765 | Modeling multi-patterning variability with statistical timing | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2015-02-03 |
| 8904329 | Systems and methods for single cell product path delay analysis | Jeanne P. Bickford, Vikram Iyengar, Brian Worth, Jinjun Xiong | 2014-12-02 |
| 8856709 | Systems and methods for correlated parameters in statistical static timing analysis | Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah +1 more | 2014-10-07 |
| 8855993 | Integrated circuit design simulation matrix interpolation | Amol A. Joshi | 2014-10-07 |
| 8850378 | Hierarchical design of integrated circuits with multi-patterning requirements | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2014-09-30 |
| 8832625 | Systems and methods for correlated parameters in statistical static timing analysis | Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah +1 more | 2014-09-09 |
| 8806402 | Modeling multi-patterning variability with statistical timing | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2014-08-12 |
| 8768679 | System and method for efficient modeling of NPskew effects on static timing tests | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett +3 more | 2014-07-01 |
| 8769452 | Parasitic extraction in an integrated circuit with multi-patterning requirements | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +4 more | 2014-07-01 |
| 8726201 | Method and system to predict a number of electromigration critical elements | Jeanne P. Bickford, Baozhen Li, Paul S. McLaughlin, Dileep N. Netrabile | 2014-05-13 |
| 8707233 | Systems and methods for correlated parameters in statistical static timing analysis | Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah +1 more | 2014-04-22 |
| 8656207 | Method for modeling variation in a feedback loop of a phase-locked loop | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman | 2014-02-18 |
| 8571825 | Design-dependent integrated circuit disposition | Jinjun Xiong, Vladimir Zolotov | 2013-10-29 |
| 8560989 | Statistical clock cycle computation | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, James C. Gregerson +6 more | 2013-10-15 |
| 8543966 | Test path selection and test program generation for performance testing integrated circuit chips | Jeanne P. Bickford, Vikram Iyengar, David E. Lackey, Jinjun Xiong | 2013-09-24 |
| 8538715 | Design-dependent integrated circuit disposition | Jinjun Xiong, Vladimir Zolotov | 2013-09-17 |
| 8539429 | System yield optimization using the results of integrated circuit chip performance path testing | Jeanne P. Bickford, Vikram Iyengar | 2013-09-17 |