Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8589843 | Method and device for selectively adding timing margin in an integrated circuit | Chandramouili Visweswariah, Paul S. Zuchowski | 2013-11-19 |
| 8543966 | Test path selection and test program generation for performance testing integrated circuit chips | Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, Jinjun Xiong | 2013-09-24 |
| 8504971 | Method and device for selectively adding timing margin in an integrated circuit | Chandramouili Visweswariah, Paul S. Zuchowski | 2013-08-06 |
| 8490040 | Disposition of integrated circuits using performance sort ring oscillator and performance path testing | Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, Jinjun Xiong | 2013-07-16 |
| 8490045 | Method and device for selectively adding timing margin in an integrated circuit | Chandramouili Visweswariah, Paul S. Zuchowski | 2013-07-16 |
| 8423847 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, Steven F. Oakland, Donald L. Wheater | 2013-04-16 |
| 8423844 | Dense register array for enabling scan out observation of both L1 and L2 latches | Pamela S. Gillis, Steven F. Oakland, Jeffery H. Oppold | 2013-04-16 |
| 8239715 | Method and apparatus for a robust embedded interface | Steven M. Eustis, Kevin W. Gorman, Michael R. Ouellette | 2012-08-07 |
| 8205124 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, Steven F. Oakland, Donald L. Wheater | 2012-06-19 |
| 8181135 | Hold transition fault model and test generation method | Vikram Iyengar, Pamela S. Gillis, Steven F. Oakland | 2012-05-15 |
| 8122409 | Method and device for selectively adding timing margin in an integrated circuit | Chandramouli Visweswariah, Paul S. Zuchowski | 2012-02-21 |
| 8117579 | LSSD compatibility for GSD unified global clock buffers | James D. Warnock, Wendel Dieter, William V. Huott, Leon Sigal, Louis Bernard Bushard +1 more | 2012-02-14 |
| 7996807 | Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method | Gary D. Grise, Vikram Iyengar, David W. Milton | 2011-08-09 |
| 7996739 | Avoiding race conditions at clock domain crossings in an edge based scan design | — | 2011-08-09 |
| 7937632 | Design structure and apparatus for a robust embedded interface | Steven M. Eustis, Kevin W. Gorman, Michael R. Ouellette | 2011-05-03 |
| 7856607 | System and method for generating at-speed structural tests to improve process and environmental parameter space coverage | Gary D. Grise, Peter A. Habitz, Vikram Iyengar, Chandramouli Visweswariah, Vladimir Zolotov | 2010-12-21 |
| 7721170 | Apparatus and method for selectively implementing launch off scan capability in at speed testing | Gary D. Grise, Vikram Iyengar, Mark R. Taylor | 2010-05-18 |
| 7620921 | IC chip at-functional-speed testing with process coverage evaluation | Eric A. Foreman, Gary D. Grise, Peter A. Habitz, Vikram Iyengar, Chandramouli Visweswariah +2 more | 2009-11-17 |
| 7560964 | Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility | Steven F. Oakland, Peter Verwegen | 2009-07-14 |
| 7529294 | Testing of multiple asynchronous logic domains | Gary D. Grise, Vikram Iyengar | 2009-05-05 |
| 7490280 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, Steven F. Oakland, Donald L. Wheater | 2009-02-10 |
| 7487487 | Design structure for monitoring cross chip delay variation on a semiconductor device | Anthony D. Polson, Theodoros E. Anemikos, Laura S. Chadwick | 2009-02-03 |
| 7482851 | Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility | Steven F. Oakland, Peter Verwegen | 2009-01-27 |
| 7484149 | Negative edge flip-flops for muxscan and edge clock compatible LSSD | — | 2009-01-27 |
| 7435990 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer | Brion Keller, Bernd Koenemann, Donald L. Wheater | 2008-10-14 |