Issued Patents All Time
Showing 1–25 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10794952 | Product performance test binning | Theodoros E. Anemikos, Susan K. Lichtensteiger, Nazmul Habib | 2020-10-06 |
| 10295592 | Pre-test power-optimized bin reassignment following selective voltage binning | Igor Arsovski, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert McMahon, Troy J. Perry +2 more | 2019-05-21 |
| 10216870 | Methodology to prevent metal lines from current pulse damage | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2019-02-26 |
| 10067184 | Product performance test binning | Theodoros E. Anemikos, Nazmul Habib, Susan K. Lichtensteiger | 2018-09-04 |
| 10013519 | Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation | Sudeep Mandal | 2018-07-03 |
| 9940430 | Burn-in power performance optimization | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2018-04-10 |
| 9865486 | Timing/power risk optimized selective voltage binning using non-linear voltage slope | Igor Arsovski, Mark W. Kuemerle, Susan K. Lichtensteiger, Jeanne H. Raymond | 2018-01-09 |
| 9852259 | Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks | Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati, Venkatasreekanth Prudvi | 2017-12-26 |
| 9791502 | On-chip usable life depletion meter and associated method | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2017-10-17 |
| 9772374 | Selective voltage binning leakage screen | Kevin K. Dezfulian, Susan K. Lichtensteiger, Jeanne H. Raymond | 2017-09-26 |
| 9767240 | Temperature-aware integrated circuit design methods and systems | Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati, Venkatasreekanth Prudvi | 2017-09-19 |
| 9759767 | Pre-test power-optimized bin reassignment following selective voltage binning | Igor Arsovski, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert McMahon, Troy J. Perry +2 more | 2017-09-12 |
| 9740815 | Electromigration-aware integrated circuit design methods and systems | Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati, Venkatasreekanth Prudvi | 2017-08-22 |
| 9653330 | Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning | John R. Goss, Robert McMahon, Troy J. Perry, Thomas G. Sopchak | 2017-05-16 |
| 9639645 | Integrated circuit chip reliability using reliability-optimized failure mechanism targeting | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2017-05-02 |
| 9625325 | System and method for identifying operating temperatures and modifying of integrated circuits | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2017-04-18 |
| 9618566 | Systems and methods to prevent incorporation of a used integrated circuit chip into a product | Nazmul Habib, Baozhen Li, Tad J. Wilder | 2017-04-11 |
| 9619609 | Integrated circuit chip design methods and systems using process window-aware timing analysis | Eric A. Foreman, Susan K. Lichtensteiger, Mark W. Kuemerle, Jeffrey G. Hemmett | 2017-04-11 |
| 9569571 | Method and system for timing violations in a circuit | Eric A. Foreman, Kerim Kalafala, Sudeep Mandal, Shashank B. Sreekanta | 2017-02-14 |
| 9557378 | Method and structure for multi-core chip product test and selective voltage binning disposition | Vikram Iyengar, Rahul K. Nadkarni, Pascal A. Nsame | 2017-01-31 |
| 9552447 | Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling | Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger | 2017-01-24 |
| 9536796 | Multiple manufacturing line qualification | Kevin K. Dezfulian, Erik L. Hedberg | 2017-01-03 |
| 9514999 | Systems and methods for semiconductor line scribe line centering | Kevin K. Dezfulian, Aurelius L. Graninger, Erik L. Hedberg, Troy J. Perry | 2016-12-06 |
| 9429619 | Reliability test screen optimization | Theodoros E. Anemikos, Douglas S. Dewey, Ernest A. Viau, Jr. | 2016-08-30 |
| 9269407 | System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time | Eric A. Foreman, Mark W. Kuemerle, Susan K. Lichtensteiger | 2016-02-23 |