VI

Vikram Iyengar

IBM: 23 patents #4,681 of 70,183Top 7%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
SI Southwest Research Institute: 1 patents #454 of 935Top 50%
Overall (All Time): #154,907 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 25 most recent of 26 patents

Patent #TitleCo-InventorsDate
10424821 Thermally regulated modular energy storage device and methods Omeed Badkoobeh 2019-09-24
9557378 Method and structure for multi-core chip product test and selective voltage binning disposition Jeanne P. Bickford, Rahul K. Nadkarni, Pascal A. Nsame 2017-01-31
9104834 Systems and methods for single cell product path delay analysis Jeanne P. Bickford, Peter A. Habitz, Brian Worth, Jinjun Xiong 2015-08-11
9058034 Integrated circuit product yield optimization using the results of performance path testing Jeanne P. Bickford, Peter A. Habitz, Jinjun Xiong 2015-06-16
9043180 Reducing power consumption during manufacturing test of an integrated circuit Animesh Khare, Kenneth Pichamuthu 2015-05-26
8996282 Fueling systems, methods and apparatus for an internal combustion engine Shizuo Sasaki, Jayant V. Sarlashkar, Gary D. Neely 2015-03-31
8904329 Systems and methods for single cell product path delay analysis Jeanne P. Bickford, Peter A. Habitz, Brian Worth, Jinjun Xiong 2014-12-02
8825433 Automatic generation of valid at-speed structural test (ASST) test groups Konda R. Baalaji, Malede W. Berhanu, Douglas C. Pricer 2014-09-02
8543966 Test path selection and test program generation for performance testing integrated circuit chips Jeanne P. Bickford, Peter A. Habitz, David E. Lackey, Jinjun Xiong 2013-09-24
8538718 Clock edge grouping for at-speed test Gary D. Grise, Douglas E. Sprague, Mark R. Taylor 2013-09-17
8539429 System yield optimization using the results of integrated circuit chip performance path testing Jeanne P. Bickford, Peter A. Habitz 2013-09-17
8490040 Disposition of integrated circuits using performance sort ring oscillator and performance path testing Jeanne P. Bickford, Peter A. Habitz, David E. Lackey, Jinjun Xiong 2013-07-16
8230283 Method to test hold path faults using functional clocking Pamela S. Gillis, Steven F. Oakland 2012-07-24
8209141 System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count Robert W. Bassett, Andrew Ferko 2012-06-26
8181135 Hold transition fault model and test generation method Pamela S. Gillis, David E. Lackey, Steven F. Oakland 2012-05-15
8176362 Online multiprocessor system reliability defect testing Monty M. Denneau, Phillip J. Nigh 2012-05-08
7996807 Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method Gary D. Grise, David E. Lackey, David W. Milton 2011-08-09
7856607 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage Gary D. Grise, Peter A. Habitz, David E. Lackey, Chandramouli Visweswariah, Vladimir Zolotov 2010-12-21
7793176 Method of increasing path coverage in transition test generation Gary D. Grise, David J. Hathaway 2010-09-07
7784000 Identifying sequential functional paths for IC testing methods and system Gary D. Grise 2010-08-24
7779375 Design structure for shutting off data capture across asynchronous clock domains during at-speed testing Gary D. Grise, Mark R. Taylor 2010-08-17
7721170 Apparatus and method for selectively implementing launch off scan capability in at speed testing Gary D. Grise, David E. Lackey, Mark R. Taylor 2010-05-18
7685542 Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing Gary D. Grise, Mark R. Taylor 2010-03-23
7620921 IC chip at-functional-speed testing with process coverage evaluation Eric A. Foreman, Gary D. Grise, Peter A. Habitz, David E. Lackey, Chandramouli Visweswariah +2 more 2009-11-17
7529294 Testing of multiple asynchronous logic domains Gary D. Grise, David E. Lackey 2009-05-05