Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8538718 | Clock edge grouping for at-speed test | Vikram Iyengar, Douglas E. Sprague, Mark R. Taylor | 2013-09-17 |
| 8423847 | Microcontroller for logic built-in self test (LBIST) | David E. Lackey, Steven F. Oakland, Donald L. Wheater | 2013-04-16 |
| 8205124 | Microcontroller for logic built-in self test (LBIST) | David E. Lackey, Steven F. Oakland, Donald L. Wheater | 2012-06-19 |
| 7996807 | Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method | Vikram Iyengar, David E. Lackey, David W. Milton | 2011-08-09 |
| 7856607 | System and method for generating at-speed structural tests to improve process and environmental parameter space coverage | Peter A. Habitz, Vikram Iyengar, David E. Lackey, Chandramouli Visweswariah, Vladimir Zolotov | 2010-12-21 |
| 7840864 | Functional frequency testing of integrated circuits | Steven F. Oakland, Anthony D. Polson, Philip Stevens | 2010-11-23 |
| 7840863 | Functional frequency testing of integrated circuits | Steven F. Oakland, Anthony D. Polson, Philip Stevens | 2010-11-23 |
| 7793176 | Method of increasing path coverage in transition test generation | David J. Hathaway, Vikram Iyengar | 2010-09-07 |
| 7784000 | Identifying sequential functional paths for IC testing methods and system | Vikram Iyengar | 2010-08-24 |
| 7779375 | Design structure for shutting off data capture across asynchronous clock domains during at-speed testing | Vikram Iyengar, Mark R. Taylor | 2010-08-17 |
| 7721170 | Apparatus and method for selectively implementing launch off scan capability in at speed testing | Vikram Iyengar, David E. Lackey, Mark R. Taylor | 2010-05-18 |
| 7698611 | Functional frequency testing of integrated circuits | Steven F. Oakland, Anthony S. Polson, Philip Stevens | 2010-04-13 |
| 7685542 | Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing | Vikram Iyengar, Mark R. Taylor | 2010-03-23 |
| 7620921 | IC chip at-functional-speed testing with process coverage evaluation | Eric A. Foreman, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Chandramouli Visweswariah +2 more | 2009-11-17 |
| 7529294 | Testing of multiple asynchronous logic domains | Vikram Iyengar, David E. Lackey | 2009-05-05 |
| 7490280 | Microcontroller for logic built-in self test (LBIST) | David E. Lackey, Steven F. Oakland, Donald L. Wheater | 2009-02-10 |
| 7290191 | Functional frequency testing of integrated circuits | Steven F. Oakland, Anthony D. Polson, Philip Stevens | 2007-10-30 |
| 7240266 | Clock control circuit for test that facilitates an at speed structural test | Henry R. Farmer, David W. Milton, Mark R. Taylor | 2007-07-03 |
| 6025992 | Integrated heat exchanger for memory module | Richard Dodge, Kenneth Haskell Earl, Douglas R. Guild, Karl D. Loughner, Jerzy M. Zalesinski | 2000-02-15 |
| 5663806 | Non-destructive target marking for image stitching | Jerzy M. Zalesinski | 1997-09-02 |
| 4870470 | Non-volatile memory cell having Si rich silicon nitride charge trapping layer | Roy Bass, Arup Bhattacharyya | 1989-09-26 |
| 4446535 | Non-inverting non-volatile dynamic RAM cell | Donald P. Gaffney, Chung H. Lam | 1984-05-01 |
| 4375085 | Dense electrically alterable read only memory | Ning Hsieh, Howard L. Kalter, Chung H. Lam | 1983-02-22 |