Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9310426 | On-going reliability monitoring of integrated circuit chips in the field | Theodoros E. Anemikos, Douglas S. Dewey, Pascal A. Nsame | 2016-04-12 |
| 9075106 | Detecting chip alterations with light emission | Kerry Bernstein, James A. Culp, David F. Heidel, Dirk Pfeiffer, Peilin Song +2 more | 2015-07-07 |
| 8336008 | Characterization of long range variability | James A. Culp, Jerry D. Hayes, Ying Liu | 2012-12-18 |
| 7962874 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2011-06-14 |
| 7890906 | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells | Laura S. Chadwick, James A. Culp, David J. Hathaway | 2011-02-15 |
| 7877714 | System and method to optimize semiconductor power by integration of physical design timing and product performance measurements | Theodoros E. Anemikos, Jeanne P. Spence Bickford, Laura S. Chadwick, Susan K. Lichtensteiger | 2011-01-25 |
| 7870525 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold | 2011-01-11 |
| 7865861 | Method of generating wiring routes with matching delay in the presence of process variation | Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2011-01-04 |
| 7849433 | Integrated circuit with uniform polysilicon perimeter density, method and design structure | Laura S. Chadwick, James A. Culp, David J. Hathaway | 2010-12-07 |
| 7840864 | Functional frequency testing of integrated circuits | Gary D. Grise, Steven F. Oakland, Philip Stevens | 2010-11-23 |
| 7840863 | Functional frequency testing of integrated circuits | Gary D. Grise, Steven F. Oakland, Philip Stevens | 2010-11-23 |
| 7823115 | Method of generating wiring routes with matching delay in the presence of process variation | Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2010-10-26 |
| 7810054 | Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point | Theodoros E. Anemikos, Jeanne P. Bickford, Laura S. Chadwick, Susan K. Lichtensteiger | 2010-10-05 |
| 7805693 | IC chip design modeling using perimeter density to electrical characteristic correlation | Laura S. Chadwick, James A. Culp | 2010-09-28 |
| 7765351 | High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips | Pascal A. Nsame, Nancy H. Pratt, Sebastian T. Ventrone | 2010-07-27 |
| 7716616 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold | 2010-05-11 |
| 7680626 | System and method of analyzing timing effects of spatial distribution in circuits | David J. Hathaway, Jerry D. Hayes | 2010-03-16 |
| 7521973 | Clock-skew tuning apparatus and method | Theodoros E. Anemikos, Michael R. Quellette | 2009-04-21 |
| 7489204 | Method and structure for chip-level testing of wire delay independent of silicon delay | Peter A. Habitz | 2009-02-10 |
| 7487487 | Design structure for monitoring cross chip delay variation on a semiconductor device | David E. Lackey, Theodoros E. Anemikos, Laura S. Chadwick | 2009-02-03 |
| 7444608 | Method and system for evaluating timing in an integrated circuit | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2008-10-28 |
| 7418689 | Method of generating wiring routes with matching delay in the presence of process variation | Peter A. Habitz, David J. Hathaway, Jerry D. Hayes | 2008-08-26 |
| 7401307 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold | 2008-07-15 |
| 7302673 | Method and system for performing shapes correction of a multi-cell reticle photomask design | Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Tad J. Wilder | 2007-11-27 |
| 7290191 | Functional frequency testing of integrated circuits | Gary D. Grise, Steven F. Oakland, Philip Stevens | 2007-10-30 |