Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8196088 | Method and structure for screening NFET-to-PFET device performance offsets within a CMOS process | — | 2012-06-05 |
| 7870525 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2011-01-11 |
| 7716616 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2010-05-11 |
| 7401307 | Slack sensitivity to parameter variation based timing analysis | Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson | 2008-07-15 |
| 7117428 | Redundancy register architecture for soft-error tolerance and methods of making the same | Michael R. Ouellette, Larry Wissell | 2006-10-03 |
| 6917221 | Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits | Kerry Bernstein, Stephen V. Kosonocky, Randy W. Mann | 2005-07-12 |
| 6778449 | Method and design for measuring SRAM array leakage macro (ALM) | Matthew J. Breitwisch, Jeffrey S. Brown, Randy W. Mann | 2004-08-17 |
| 6420746 | Three device DRAM cell with integrated capacitor and local interconnect | John A. Bracchitta, Randy W. Mann | 2002-07-16 |