Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7630915 | Intellectual property management method and apparatus | Patricia McGuiness Marmillion, Bernadette Ann Pierson, Henry Charles Rickers, Howard J. Walter, Jr. | 2009-12-08 |
| 7323382 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Kerry Bernstein, William J. Cote, Tak H. Ning, Wilbur D. Pricer | 2008-01-29 |
| 7195971 | Method of manufacturing an intralevel decoupling capacitor | Kerry Bernstein, William J. Cote, Tak H. Ning, Wilbur D. Pricer | 2007-03-27 |
| 7089192 | Intellectual property management method and apparatus | Patricia Marmillion, Bernadette Ann Pierson, Henry Charles Rickers, Howard J. Walter, Jr. | 2006-08-08 |
| 6882015 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Kerry Bernstein, William J. Cote, Tak H. Ning, Wilbur D. Pricer | 2005-04-19 |
| 6858889 | Polysilicon capacitor having large capacitance and low resistance | James W. Adkisson, Jed H. Rankin, Anthony K. Stamper | 2005-02-22 |
| 6677637 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Kerry Bernstein, William J. Cote, Tak H. Ning, Wilbur D. Pricer | 2004-01-13 |
| 6660596 | Double planar gated SOI MOSFET structure | James W. Adkisson, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson +1 more | 2003-12-09 |
| 6483156 | Double planar gated SOI MOSFET structure | James W. Adkisson, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson +1 more | 2002-11-19 |
| 6420746 | Three device DRAM cell with integrated capacitor and local interconnect | Randy W. Mann, Jeffrey H. Oppold | 2002-07-16 |
| 6394638 | Trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White | 2002-05-28 |
| 6373095 | NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area | James S. Nakos | 2002-04-16 |
| 6344381 | Method for forming pillar CMOS | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2002-02-05 |
| 6339015 | Method of fabricating a non-volatile semiconductor device | James S. Nakos | 2002-01-15 |
| 6261895 | Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor | James W. Adkisson, Jed H. Rankin, Anthony K. Stamper | 2001-07-17 |
| 6255699 | Pillar CMOS structure | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2001-07-03 |
| 6232633 | NVRAM cell using sharp tip for tunnel erase | James S. Nakos | 2001-05-15 |
| 6130469 | Electrically alterable antifuse using FET | Wilbur D. Pricer | 2000-10-10 |
| 6100123 | Pillar CMOS structure | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2000-08-08 |
| 6063687 | Formation of trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White | 2000-05-16 |
| 6060358 | Damascene NVRAM cell and method of manufacture | Jeffrey B. Johnson, Glen L. Miles | 2000-05-09 |
| 6020777 | Electrically programmable anti-fuse circuit | Wilbur D. Pricer | 2000-02-01 |
| 5949265 | Soft latch circuit having sharp-cornered hysteresis characteristics | Michel S. Michail, Wilbur D. Pricer | 1999-09-07 |
| 5734192 | Trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White | 1998-03-31 |
| 5518945 | Method of making a diffused lightly doped drain device with built in etch stop | Gabriel Hartstein, Stephen A. Mongeon, Anthony C. Speranza | 1996-05-21 |