Issued Patents All Time
Showing 25 most recent of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8772876 | High-voltage silicon-on-insulator transistors and methods of manufacturing the same | William H. Ma, Carl Radens, William R. Tonti | 2014-07-08 |
| 8610244 | Layered structure with fuse | Louis Lu-Chen Hsu, William R. Tonti, Chih-Chao Yang | 2013-12-17 |
| 8598641 | Sea-of-fins structure on a semiconductor substrate and method of fabrication | Howard H. Chen, Louis C. Hsu, Chun-Yung Sung | 2013-12-03 |
| 8587062 | Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts | Haining Yang | 2013-11-19 |
| 8580646 | Method of fabricating field effect transistors with low k sidewall spacers | Kangguo Cheng, Louis L. Hsu, William R. Tonti | 2013-11-12 |
| 8536632 | FinFET with reduced gate to fin overlay sensitivity | Kangguo Cheng, Louis L. Hsu, John E. Sheets, II | 2013-09-17 |
| 8518767 | FinFET with reduced gate to fin overlay sensitivity | Kangguo Cheng, Louis L. Hsu, John E. Sheets, II | 2013-08-27 |
| 8300452 | Structure and method for improving storage latch susceptibility to single event upsets | Ethan H. Cannon, Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III | 2012-10-30 |
| 8232620 | Electronic fuses in semiconductor integrated circuits | Louis Lu-Chen Hsu, William R. Tonti, Chih-Chao Yang | 2012-07-31 |
| 8179694 | Magnetic induction grid as an early warning mechanism for space based microelectronics | Mark A. Bransford | 2012-05-15 |
| 8120095 | High-density, trench-based non-volatile random access SONOS memory SOC applications | Herbert L. Ho, Tak H. Ning, Yoichi Otani | 2012-02-21 |
| 8076190 | Sea-of-fins structure on a semiconductor substrate and method of fabrication | Howard H. Chen, Louis C. Hsu, Chun-Yung Sung | 2011-12-13 |
| 8008713 | Vertical SOI trench SONOS cell | David M. Dobuzinsky, Herbert L. Ho, Yoichi Otani | 2011-08-30 |
| 7984408 | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering | Kangguo Cheng, Louis L. Hsu, Haining Yang | 2011-07-19 |
| 7984409 | Structures incorporating interconnect structures with improved electromigration resistance | Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2011-07-19 |
| 7977766 | Trench anti-fuse structures for a programmable integrated circuit | Roger A. Booth, Jr., Kangguo Cheng, William R. Tonti | 2011-07-12 |
| 7965540 | Structure and method for improving storage latch susceptibility to single event upsets | Ethan H. Cannon, Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III | 2011-06-21 |
| 7948084 | Dielectric material with a reduced dielectric constant and methods of manufacturing the same | Louis L. Hsu, Chih-Chao Yang | 2011-05-24 |
| 7947566 | Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate | Howard H. Chen, Louis L. Hsu | 2011-05-24 |
| 7928436 | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods | Kangguo Cheng, Brian J. Greene | 2011-04-19 |
| 7916531 | Memory elements and methods of using the same | Wagdi W. Abadeer, Anthony R. Bonaccio, William R. Tonti, Sebastian T. Ventrone | 2011-03-29 |
| 7915682 | Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures | Louis L. Hsu | 2011-03-29 |
| 7911025 | Fuse/anti-fuse structure and methods of making and programming same | Louis C. Hsu, Rajiv V. Joshi, Chih-Chao Yang | 2011-03-22 |
| 7906390 | Thin gate electrode CMOS devices and methods of fabricating same | William R. Tonti | 2011-03-15 |
| 7898014 | Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures | Kangguo Cheng, Louis L. Hsu | 2011-03-01 |