Issued Patents All Time
Showing 51–75 of 440 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7767541 | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods | Kangguo Cheng, Brian J. Greene | 2010-08-03 |
| 7759191 | Vertical SOI transistor memory cell and method of forming the same | Kangguo Cheng | 2010-07-20 |
| 7754513 | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures | William R. Tonti | 2010-07-13 |
| 7750406 | Design structure incorporating a hybrid substrate | Ethan H. Cannon, Toshiharu Furukawa, John G. Gaudiello, Mark C. Hakey, Steven J. Holmes +3 more | 2010-07-06 |
| 7737530 | Semiconductor device structures for bipolar junction transistors and methods of fabricating such structures | Kangguo Cheng, Louis L. Hsu | 2010-06-15 |
| 7737504 | Well isolation trenches (WIT) for CMOS devices | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, William R. Tonti | 2010-06-15 |
| 7732322 | Dielectric material with reduced dielectric constant and methods of manufacturing the same | Louis L. Hsu, Chih-Chao Yang | 2010-06-08 |
| 7728371 | SOI CMOS compatible multiplanar capacitor | Kangguo Cheng, Louis C. Hsu, William R. Tonti | 2010-06-01 |
| 7727848 | Methods and semiconductor structures for latch-up suppression using a conductive region | Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, William R. Tonti | 2010-06-01 |
| 7700466 | Tunneling effect transistor with self-aligned gate | Roger A. Booth, Jr., Kangguo Cheng | 2010-04-20 |
| 7692250 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures | Roger A. Booth, Jr., William R. Tonti | 2010-04-06 |
| 7691712 | Semiconductor device structures incorporating voids and methods of fabricating such structures | Dureseti Chidambarrao, Ricardo A. Donaton | 2010-04-06 |
| 7687865 | Method and structure to reduce contact resistance on thin silicon-on-insulator device | Brian J. Greene, Louis L. Hsu, Chun-Yung Sung | 2010-03-30 |
| 7672105 | Production of limited lifetime devices achieved through E-fuses | John Michael Borkenhagen, William Paul Hovis, Daniel P. Kolz | 2010-03-02 |
| 7667248 | Bulk FinFET device | Roger A. Booth, Jr., William Paul Hovis | 2010-02-23 |
| 7666781 | Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures | Louis L. Hsu, William R. Tonti, Chih-Chao Yang | 2010-02-23 |
| 7659599 | Patterned silicon-on-insulator layers and methods for forming the same | Roger A. Booth, Jr., Louis L. Hsu, William R. Tonti | 2010-02-09 |
| 7659178 | Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate | Kangguo Cheng, Louis L. Hsu, Haining Yang | 2010-02-09 |
| 7659168 | eFuse and methods of manufacturing the same | Louis L. Hsu, William R. Tonti | 2010-02-09 |
| 7656005 | Electrically programmable π-shaped fuse structures and methods of fabrication thereof | Roger A. Booth, Jr., Kangguo Cheng, William R. Tonti | 2010-02-02 |
| 7655985 | Methods and semiconductor structures for latch-up suppression using a conductive region | Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, William R. Tonti | 2010-02-02 |
| 7651929 | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates | Louis L. Hsu, William R. Tonti | 2010-01-26 |
| 7651902 | Hybrid substrates and methods for forming such hybrid substrates | Ethan H. Cannon, Toshiharu Furukawa, John G. Gaudiello, Mark C. Hakey, Steven J. Holmes +3 more | 2010-01-26 |
| 7648869 | Method of fabricating semiconductor structures for latch-up suppression | Shunhua T. Chang, Toshiharu Furukawa, Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III +1 more | 2010-01-19 |
| 7645676 | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures | Toshiharu Furukawa, Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III, William R. Tonti | 2010-01-12 |