Issued Patents All Time
Showing 1–25 of 286 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10589445 | Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate | Mark C. Hakey, David V. Horak, Peter H. Mitchell, William P. Parker, William R. Tonti | 2020-03-17 |
| 9263517 | Extremely thin semiconductor-on-insulator (ETSOI) layer | Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Robert J. Gauthier, Jr., Jed H. Rankin +2 more | 2016-02-16 |
| 9059203 | Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure | Robert R. Robison, Richard Q. Williams | 2015-06-16 |
| 9018024 | Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness | Nathaniel Berliner, Kangguo Cheng, Jason E. Cummings, Jed H. Rankin, Robert R. Robison +1 more | 2015-04-28 |
| 8940554 | Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness | Nathaniel Berliner, Kangguo Cheng, Douglas C. La Tulipe, Jr., William R. Tonti | 2015-01-27 |
| 8933559 | Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules | Veeraraghavan S. Basker, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III, Krishna V. Singh | 2015-01-13 |
| 8900961 | Selective deposition of germanium spacers on nitride | Ashima B. Chakravarti, Anthony I. Chou, Steven J. Holmes, Wesley C. Natzle | 2014-12-02 |
| 8697561 | Microelectronic structure by selective deposition | Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2014-04-15 |
| 8674476 | Anti-fuse device structure and electroplating circuit structure and method | Veeraraghavan S. Basker, William R. Tonti | 2014-03-18 |
| 8610211 | Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure | Robert R. Robison, Richard Q. Williams | 2013-12-17 |
| 8568604 | CMOS gate structures fabricated by selective oxidation | Bruce B. Doris, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2013-10-29 |
| 8546920 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Wilfried Haensch, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight | 2013-10-01 |
| 8541823 | Field effect transistor | Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2013-09-24 |
| 8525186 | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor | Kangguo Cheng, Johnathan E. Faltermeier, Xuefeng Hua | 2013-09-03 |
| 8450806 | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby | Charles W. Koburger, III, James A. Slinkman | 2013-05-28 |
| 8420476 | Integrated circuit with finFETs and MIM fin capacitor | Roger A. Booth, Jr., Kangguo Cheng, Chengwen Pei | 2013-04-16 |
| 8361872 | High performance low power bulk FET device and method of manufacture | Jin Cai, Robert R. Robison | 2013-01-29 |
| 8299605 | Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules | Veeraraghavan S. Basker, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III, Krishna V. Singh | 2012-10-30 |
| 8300452 | Structure and method for improving storage latch susceptibility to single event upsets | Ethan H. Cannon, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman | 2012-10-30 |
| 8288826 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Wilfried Haensch, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight | 2012-10-16 |
| 8242578 | Anti-fuse device structure and electroplating circuit structure and method | Veeraraghavan S. Basker, William R. Tonti | 2012-08-14 |
| 8183159 | Device component forming method with a trim step prior to sidewall image transfer (SIT) processing | David V. Horak, Charles W. Koburger, III, Qiqing C. Quyang | 2012-05-22 |
| 8138100 | Microelectronic structure by selective deposition | Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2012-03-20 |
| 8124427 | Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness | Nathaniel Berliner, Kangguo Cheng, Douglas C. La Tulipe, Jr., William R. Tonti | 2012-02-28 |
| 8110483 | Forming an extremely thin semiconductor-on-insulator (ETSOI) layer | Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Robert J. Gauthier, Jr., Jed H. Rankin +2 more | 2012-02-07 |