TF

Toshiharu Furukawa

IBM: 278 patents #88 of 70,183Top 1%
TO Toyota: 3 patents #8,352 of 26,838Top 35%
SC Sekisui Chemical Co.: 2 patents #358 of 908Top 40%
DT Daido Tokushuko: 1 patents #152 of 382Top 40%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
TC Tomoeagawa Paper Co.: 1 patents #110 of 226Top 50%
📍 South Burlington, VT: #3 of 1,136 inventorsTop 1%
🗺 Vermont: #7 of 4,968 inventorsTop 1%
Overall (All Time): #1,485 of 4,157,543Top 1%
286
Patents All Time

Issued Patents All Time

Showing 51–75 of 286 patents

Patent #TitleCo-InventorsDate
7838943 Shared gate for conventional planar device and horizontal CNT Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters 2010-11-23
7829883 Vertical carbon nanotube field effect transistors and arrays Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell +1 more 2010-11-09
7825525 Layout and process to contact sub-lithographic structures Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chung H. Lam 2010-11-02
7820502 Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell +1 more 2010-10-26
7816743 Microelectronic structure by selective deposition Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2010-10-19
7791145 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III, Jack A. Mandelman, William R. Tonti 2010-09-07
7786583 Integrated circuit chip utilizing oriented carbon nanotube conductive layers Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell 2010-08-31
7776680 Complementary metal oxide semiconductor device with an electroplated metal replacement gate Veeraraghavan S. Basker, John M. Cotte, Hariklia Deligianni, Vamsi K. Paruchuri, William R. Tonti 2010-08-17
7771604 Reduced mask count gate conductor definition Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2010-08-10
7750406 Design structure incorporating a hybrid substrate Ethan H. Cannon, John G. Gaudiello, Mark C. Hakey, Steven J. Holmes, David V. Horak +3 more 2010-07-06
7737504 Well isolation trenches (WIT) for CMOS devices Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman, William R. Tonti 2010-06-15
7732865 Epitaxial imprinting Carl Radens, William R. Tonti, Richard Q. Williams 2010-06-08
7727848 Methods and semiconductor structures for latch-up suppression using a conductive region David V. Horak, Charles W. Koburger, III, Jack A. Mandelman, William R. Tonti 2010-06-01
7704855 Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby Charles W. Koburger, III, James A. Slinkman 2010-04-27
7705385 Selective deposition of germanium spacers on nitride Ashima B. Chakravarti, Anthony I. Chou, Steven J. Holmes, Wesley C. Natzle 2010-04-27
7699996 Sidewall image transfer processes for forming multiple line-widths John G. Gaudiello, Mark C. Hakey, David V. Horak, Charles W. Koburger, III 2010-04-20
7691720 Vertical nanotube semiconductor device structures and methods of forming the same Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell +1 more 2010-04-06
7674674 Method of forming a dual gated FinFET gain cell Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Mark E. Masters, Peter H. Mitchell 2010-03-09
7671413 SOI device with reduced junction capacitance 2010-03-02
7668004 Non-volatile switching and memory devices using vertical nanotubes Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2010-02-23
7659171 Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2010-02-09
7655985 Methods and semiconductor structures for latch-up suppression using a conductive region David V. Horak, Charles W. Koburger, III, Jack A. Mandelman, William R. Tonti 2010-02-02
7652334 Shallow trench isolation formation Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2010-01-26
7651902 Hybrid substrates and methods for forming such hybrid substrates Ethan H. Cannon, John G. Gaudiello, Mark C. Hakey, Steven J. Holmes, David V. Horak +3 more 2010-01-26
7648869 Method of fabricating semiconductor structures for latch-up suppression Shunhua T. Chang, Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III, Jack A. Mandelman +1 more 2010-01-19