Issued Patents All Time
Showing 25 most recent of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10546936 | Structure for reduced source and drain contact to gate stack capacitance | Carl Radens | 2020-01-28 |
| 10439046 | Structure and method for improving access resistance in U-channel ETSOI | Robert H. Dennard, Rajiv V. Joshi | 2019-10-08 |
| 10374046 | Structure for reduced source and drain contact to gate stack capacitance | Carl Radens | 2019-08-06 |
| 10269905 | Structure for reduced source and drain contact to gate stack capacitance | Carl Radens | 2019-04-23 |
| 9825172 | Field effect transistor structure and method of forming same | Edward J. Nowak | 2017-11-21 |
| 9755030 | Method for reduced source and drain contact to gate stack capacitance | Carl Radens | 2017-09-05 |
| 9646124 | Modeling transistor performance considering non-uniform local layout effects | Dureseti Chidambarrao | 2017-05-09 |
| 9601570 | Structure for reduced source and drain contact to gate stack capacitance | Carl Radens | 2017-03-21 |
| 9373678 | Non-planar capacitors with finely tuned capacitance values and methods of forming the non-planar capacitors | Edward J. Nowak | 2016-06-21 |
| 9178012 | Plated trench capacitor structures | Veeraraghavan S. Basker | 2015-11-03 |
| 9059203 | Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure | Toshiharu Furukawa, Robert R. Robison | 2015-06-16 |
| 9058441 | Methods for modeling of FinFET width quantization | Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang | 2015-06-16 |
| 8835261 | Field effect transistor structure and method of forming same | Edward J. Nowak | 2014-09-16 |
| 8806419 | Apparatus for modeling of FinFET width quantization | Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang | 2014-08-12 |
| 8799848 | Methods for modeling of FinFET width quantization | Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang | 2014-08-05 |
| 8745571 | Analysis of compensated layout shapes | Hongmei Li | 2014-06-03 |
| 8703572 | Embeded DRAM cell structures with high conductance electrodes and methods of manufacture | Veeraraghavan S. Basker | 2014-04-22 |
| 8610211 | Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure | Toshiharu Furukawa, Robert R. Robison | 2013-12-17 |
| 8453100 | Circuit analysis using transverse buckets | Dureseti Chidambarrao | 2013-05-28 |
| 8417503 | System and method for target-based compact modeling | Kerry Bernstein, Josef S. Watts | 2013-04-09 |
| 8392867 | System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists | Yanqing Deng, Paul A. Hyde, James M. Johnson, Todd G. McKenzie, Scott K. Springer | 2013-03-05 |
| 8211741 | Carbon nanotube based integrated semiconductor circuit | Joerg Appenzeller, AJ KleinOsowski, Edward J. Nowak | 2012-07-03 |
| 8119474 | High performance capacitors in planar back gates CMOS | Andres Bryant, Edward J. Nowak | 2012-02-21 |
| 8112729 | Method and system for selective stress enablement in simulation modeling | William R. Tonti | 2012-02-07 |
| 8037433 | System and methodology for determining layout-dependent effects in ULSI simulation | Dureseti Chidambarrao, Tong Li, David W. Winston | 2011-10-11 |