Issued Patents All Time
Showing 1–25 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402349 | Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Ayan Kar +5 more | 2025-08-26 |
| 12328947 | Substrate-less silicon controlled rectifier (SCR) integrated circuit structures | Rui Ma, Kalyan C. Kolluru, Nicholas A. Thomson, Ayan Kar, Benjamin Orr +3 more | 2025-06-10 |
| 12328920 | Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy | William Hsu, Biswajeet Guha, Anand S. Murthy, Tahir Ghani | 2025-06-10 |
| 12317590 | Substrate-free integrated circuit structures | Biswajeet Guha, Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr +9 more | 2025-05-27 |
| 12294006 | Gate-all-around integrated circuit structures having insulator substrate | Biswajeet Guha, William Hsu, Stephen M. Cea, Tahir Ghani | 2025-05-06 |
| 12288789 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more | 2025-04-29 |
| 12272737 | Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Tahir Ghani | 2025-04-08 |
| 12166031 | Substrate-less electrostatic discharge (ESD) integrated circuit structures | Biswajeet Guha, Brian J. Greene, Daniel Schulman, William Hsu, Curtis Tsai +1 more | 2024-12-10 |
| 11908856 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more | 2024-02-20 |
| 11869987 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Biswajeet Guha +2 more | 2024-01-09 |
| 11837641 | Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more | 2023-12-05 |
| 11824116 | Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Ayan Kar +5 more | 2023-11-21 |
| 11799009 | Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact | Biswajeet Guha, William Hsu, Kinyip Phoa, Oleg Golonzka, Tahir Ghani | 2023-10-24 |
| 11417781 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Biswajeet Guha +2 more | 2022-08-16 |
| 11101357 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2021-08-24 |
| 10734492 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2020-08-04 |
| 10600680 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Michael A. Guillorn, HsinYu Tsai | 2020-03-24 |
| 10580894 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2020-03-03 |
| 10381452 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-08-13 |
| 10374048 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-08-06 |
| 10367072 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-07-30 |
| 10256139 | Chemoepitaxy etch trim using a self aligned hard mask for metal line to via | Markus Brink, Michael A. Guillorn, HsinYu Tsai | 2019-04-09 |
| 10083880 | Hybrid ETSOI structure to minimize noise coupling from TSV | Yu-Shiang Lin, Shih-Hsien Lo, Joel A. Silberman | 2018-09-25 |
| 10056487 | Strained semiconductor nanowire | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2018-08-21 |
| 10014214 | Electronic device including moat power metallization in trench | Josephine B. Chang, Leland Chang, Michael A. Guillorn, Adam M. Pyzyna | 2018-07-03 |