Issued Patents All Time
Showing 25 most recent of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12040250 | Heat pipe for vertically stacked field effect transistors | Terence B. Hook, Brent A. Anderson | 2024-07-16 |
| 11894361 | Co-integrated logic, electrostatic discharge, and well contact devices on a substrate | Julien Frougier, Sagarika Mukesh, Andrew M. Greene, Ruilong Xie, Veeraraghavan S. Basker +4 more | 2024-02-06 |
| 11101357 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2021-08-24 |
| 10734492 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2020-08-04 |
| 10580686 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2020-03-03 |
| 10381452 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-08-13 |
| 10374048 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-08-06 |
| 10367072 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2019-07-30 |
| 10256152 | Methods of making FinFET device comprising a piezoelectric liner for generating a surface charge | Qun Gao, Naved Siddiqui | 2019-04-09 |
| 10242906 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2019-03-26 |
| 10049942 | Asymmetric semiconductor device and method of forming same | Judson R. Holt, Arvind Kumar, Henry K. Utomo | 2018-08-14 |
| 10032862 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2018-07-24 |
| 10014364 | On-chip resistors with a tunable temperature coefficient of resistance | Qun Gao, Stephen Furkay, Naved Siddiqui | 2018-07-03 |
| 9923082 | Junction butting structure using nonuniform trench shape | Judson R. Holt, Arvind Kumar, Henry K. Utomo | 2018-03-20 |
| 9922831 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-03-20 |
| 9859122 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-01-02 |
| 9837319 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-12-05 |
| 9768071 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-09-19 |
| 9768195 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2017-09-19 |
| 9721843 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-08-01 |
| 9703301 | Methods and control systems of resistance adjustment of resistors | Arvind Kumar, Sungjae Lee | 2017-07-11 |
| 9698159 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2017-07-04 |
| 9685379 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-06-20 |
| 9659961 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2017-05-23 |
| 9627480 | Junction butting structure using nonuniform trench shape | Judson R. Holt, Arvind Kumar, Henry K. Utomo | 2017-04-18 |