Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9595518 | Fin-type metal-semiconductor resistors and fabrication methods thereof | Chengwen Pei, Edward P. Maciejewski, Ning Zhan | 2017-03-14 |
| 9577061 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-02-21 |
| 9570354 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-02-14 |
| 9559010 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-01-31 |
| 9543213 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-01-10 |
| 9530798 | High performance heat shields with reduced capacitance | Sungjae Lee, Joseph M. Lukaitis, Robert R. Robison | 2016-12-27 |
| 9508826 | Replacement gate structure for enhancing conductivity | Arvind Kumar, Sungjae Lee | 2016-11-29 |
| 9484246 | Buried signal transmission line | Arvind Kumar, Sungjae Lee, Richard A. Wachnik | 2016-11-01 |
| 9450072 | Replacement gate structure for enhancing conductivity | Arvind Kumar, Sungjae Lee | 2016-09-20 |
| 9425079 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2016-08-23 |
| 9412667 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2016-08-09 |
| 9412759 | CMOS gate contact resistance reduction | Arvind Kumar, Sungjae Lee | 2016-08-09 |
| 9401325 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2016-07-26 |
| 9400511 | Methods and control systems of resistance adjustment of resistors | Arvind Kumar, Sungjae Lee | 2016-07-26 |
| 9269786 | Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors | Arvind Kumar, Shreesh Narasimha, Claude Ortolland, Kai Zhao | 2016-02-23 |
| 9219059 | Semiconductor structure with integrated passive structures | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2015-12-22 |
| 9190418 | Junction butting in SOI transistor with embedded source/drain | Murshed Chowdhury, Arvind Kumar, Robert R. Robison | 2015-11-17 |
| 9064972 | Method of forming a gated diode structure for eliminating RIE damage from cap removal | Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher | 2015-06-23 |
| 8963228 | Non-volatile memory device integrated with CMOS SOI FET on a single chip | Arvind Kumar | 2015-02-24 |
| 8900961 | Selective deposition of germanium spacers on nitride | Ashima B. Chakravarti, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle | 2014-12-02 |
| 8829616 | Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage | Murshed Chowdhury, Arvind Kumar, Shreesh Narasimha | 2014-09-09 |
| 8816473 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Arvind Kumar, Renee T. Mo, Shreesh Narasimha | 2014-08-26 |
| 8779551 | Gated diode structure for eliminating RIE damage from cap removal | Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher | 2014-07-15 |
| 8667448 | Integrated circuit having local maximum operating voltage | Arvind Kumar, Renee T. Mo | 2014-03-04 |
| 8558313 | Bulk substrate FET integrated on CMOS SOI | Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang | 2013-10-15 |