Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RR

Robert R. Robison — 146 Patents

IBM: 128 patents #374 of 70,183Top 1%
Globalfoundries: 13 patents #279 of 4,424Top 7%
TETessera: 3 patents #129 of 271Top 50%
ETElpis Technologies: 1 patents #31 of 121Top 30%
GUGlobalfoundries U.S.: 1 patents #363 of 211Top 175%
Rexford, NY: #1 of 148 inventorsTop 1%
New York: #267 of 115,490 inventorsTop 1%
Overall (All Time): #6,592 of 4,157,543Top 1%
146 Patents All Time
Robert R. Robison has been granted 146 US patents while listed as an inventor at IBM. The first was granted in 2010 and the most recent in September 2025. Robert R. Robison ranks #6,592 of 4,157,543 US inventors in our database (top 0.16%). Patent records list Robert R. Robison in Rexford, NY, US.

Issued Patents All Time

Showing 1–25 of 146 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12432960 Wraparound contact with reduced distance to channel Ruilong Xie, Reinaldo Vega, Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker +2 more 2025-09-30
12402546 Composite material phase change memory cell Timothy Mathew Philip, Kevin W. Brew, Caitlin Camille Stuckey, Rebecca Martin, Lawrence A. Clevenger 2025-08-26
12402391 Stressed material within gate cut region Huimei Zhou, Andrew M. Greene, Michael P. Belyansky, Oleg Gluschenkov, Juntao Li +2 more 2025-08-26
12356685 Looped long channel field-effect transistor Ruilong Xie, Ardasheir Rahman, Hemanth Jagannathan, Brent A. Anderson, Heng Wu 2025-07-08
12268030 Self-aligned C-shaped vertical field effect transistor Ruilong Xie, Hemanth Jagannathan, Jay William Strane 2025-04-01
12243819 Single-mask alternating line deposition Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2025-03-04
12062703 Self aligned replacement metal source/drain FINFET Emre Alptekin, Reinaldo Vega 2024-08-13 $11,084,000
12015069 Gate-all-around field effect transistor having multiple threshold voltages Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Reinaldo Vega, Tenko Yamashita 2024-06-18 $16,708,000
11990410 Top via interconnect having a line with a reduced bottom dimension Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2024-05-21 $15,464,000
11961759 Interconnects having spacers for improved top via critical dimension and overlay tolerance Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2024-04-16 $17,011,000
11894265 Top via with damascene line and via Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny 2024-02-06 $12,408,000
11869808 Top via process with damascene metal Lawrence A. Clevenger, Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2024-01-09 $9,963,000
11869936 Semiconductor device and method of forming the semiconductor device Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more 2024-01-09 $9,963,000
11869937 Semiconductor device and method of forming the semiconductor device Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more 2024-01-09 $9,963,000
11854884 Fully aligned top vias Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Lawrence A. Clevenger 2023-12-26 $6,691,000
11823998 Top via with next level line selective growth Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi 2023-11-21 $7,457,000
11804406 Top via cut fill process for line extension reduction Christopher J. Penny, Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo 2023-10-31 $8,788,000
11791258 Conductive lines with subtractive cuts Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny 2023-10-17 $7,011,000
11757012 Source and drain contact cut last process to enable wrap-around-contact Andrew M. Greene, Dechao Guo, Tenko Yamashita, Veeraraghavan S. Basker, Ardasheir Rahman 2023-09-12 $5,734,000
11682617 High aspect ratio vias for integrated circuits Nicholas Anthony Lanzillo, Somnath Ghosh, Lawrence A. Clevenger 2023-06-20 $4,843,000
11670542 Stepped top via for via resistance reduction Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2023-06-06 $14,513,000
11621189 Barrier-less prefilled via formation Nicholas Anthony Lanzillo, Hosadurga Shobha, Junli Wang, Lawrence A. Clevenger, Christopher J. Penny +1 more 2023-04-04 $5,091,000
11600565 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2023-03-07 $13,230,000
11527434 Line cut patterning using sacrificial material Timothy Mathew Philip, Daniel James Dechene, Somnath Ghosh 2022-12-13 $8,590,000
11437317 Single-mask alternating line deposition Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2022-09-06 $10,660,000