RR

Robert R. Robison

IBM: 128 patents #372 of 70,183Top 1%
Globalfoundries: 13 patents #279 of 4,424Top 7%
TE Tessera: 3 patents #129 of 271Top 50%
ET Elpis Technologies: 1 patents #31 of 121Top 30%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
📍 Rexford, NY: #1 of 148 inventorsTop 1%
🗺 New York: #263 of 115,490 inventorsTop 1%
Overall (All Time): #6,545 of 4,157,543Top 1%
146
Patents All Time

Issued Patents All Time

Showing 26–50 of 146 patents

Patent #TitleCo-InventorsDate
11430735 Barrier removal for conductor in top via integration scheme Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi 2022-08-30
11380836 Topological qubit device Steven J. Holmes, Timothy Mathew Philip, Sagarika Mukesh, Youngseok Kim, Devendra K. Sadana 2022-07-05
11342446 Nanosheet field effect transistors with partial inside spacers Michael A. Guillorn, Terence B. Hook, Reinaldo Vega, Rajasekhar Venigalla 2022-05-24
11335850 Magnetoresistive random-access memory device including magnetic tunnel junctions Karthik Yogendra, Eric Raymond Evarts 2022-05-17
11302575 Subtractive line with damascene second line type Brent A. Anderson, Christopher J. Penny, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi 2022-04-12
11295978 Interconnects having spacers for improved top via critical dimension and overlay tolerance Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2022-04-05
11289371 Top vias with selectively retained etch stops Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi 2022-03-29
11276639 Conductive lines with subtractive cuts Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny 2022-03-15
11276611 Top via on subtractively etched conductive line Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny 2022-03-15
11245020 Gate-all-around field effect transistor having multiple threshold voltages Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Reinaldo Vega, Tenko Yamashita 2022-02-08
11239316 Semiconductor device and method of forming the semiconductor device Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more 2022-02-01
11232977 Stepped top via for via resistance reduction Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2022-01-25
11217481 Fully aligned top vias Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Lawrence A. Clevenger 2022-01-04
11195795 Well-controlled edge-to-edge spacing between adjacent interconnects Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2021-12-07
11195792 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo 2021-12-07
11189568 Top via interconnect having a line with a reduced bottom dimension Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2021-11-30
11177166 Etch stop layer removal for capacitance reduction in damascene top via integration Christopher J. Penny, Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo 2021-11-16
11177160 Double patterned lithography using spacer assisted cuts for patterning steps Timothy Mathew Philip, Somnath Ghosh 2021-11-16
11171084 Top via with next level line selective growth Brent A. Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi 2021-11-09
11164777 Top via with damascene line and via Lawrence A. Clevenger, Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny 2021-11-02
11158537 Top vias with subtractive line formation Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi 2021-10-26
11158536 Patterning line cuts before line patterning using sacrificial fill material Daniel James Dechene, Timothy Mathew Philip, Somnath Ghosh 2021-10-26
11152464 Self-aligned isolation for nanosheet transistor Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker 2021-10-19
11152299 Hybrid selective dielectric deposition for aligned via integration Nicholas Anthony Lanzillo, Christopher J. Penny, Hosadurga Shobha, Lawrence A. Clevenger 2021-10-19
11152257 Barrier-less prefilled via formation Nicholas Anthony Lanzillo, Hosadurga Shobha, Junli Wang, Lawrence A. Clevenger, Christopher J. Penny +1 more 2021-10-19